how can i fix this problem ?
Error (10170): Verilog HDL syntax error at adc.v(2) near text ";"; expecting ".", or an identifier
the coding are for ...
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how can i fix this problem ?
Error (10170): Verilog HDL syntax error at adc.v(2) near text ";"; expecting ".", or an identifier
the coding are for ADC implementation on FPGA.
You have written code in VHDL HDL & saved that with verilog extension (*.v), just perform 'Save As..' & save the new file with (*.vhd)extension & remove this abc.v file from project.
