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i have problems: How to creat noise gaussian or normal noise in vhdl ??? and how to simulate sine wave and sin wave+ noise in modelsim altera
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--- Quote Start --- i have problems: How to creat noise gaussian or normal noise in vhdl ??? and how to simulate sine wave and sin wave+ noise in modelsim altera --- Quote End --- shift register based prbs can generate pseudo random noise. LUTs also can be used to store whatever type of noise you get from tools like matlab e.g. gaussian. You add noise signal to your signal sample by sample. sine wave can be generated from luts by hand or nco compiler.
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--- Quote Start --- shift register based prbs can generate pseudo random noise. LUTs also can be used to store whatever type of noise you get from tools like matlab e.g. gaussian. You add noise signal to your signal sample by sample. sine wave can be generated from luts by hand or nco compiler. --- Quote End --- how LUTs can store signal ,and how to convert gaussan from matlab to vhdl,i đon't understand ??? how can generate sine wave by LUTs( i know nco blocks)
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--- Quote Start --- how LUTs can store signal --- Quote End --- insert your data in mif files for ram to play --- Quote Start --- and how to convert gaussan from matlab to vhdl,i đon't understand ??? --- Quote End --- I didn't say that. you create mif file from data --- Quote Start --- how can generate sine wave by LUTs( i know nco blocks) --- Quote End --- use nco compiler, that does it all for you You will need to make some research for all that before diving as it seems you are a beginner
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Are you talking about creating noise only for simulation, or from an FPGA?
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--- Quote Start --- insert your data in mif files for ram to play I didn't say that. you create mif file from data use nco compiler, that does it all for you You will need to make some research for all that before diving as it seems you are a beginner --- Quote End --- yeah,i'm a beginner,need to learn more
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--- Quote Start --- Are you talking about creating noise only for simulation, or from an FPGA? --- Quote End --- just for simulation,thanks
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VHDL does have a "uniform" function in the math_real package than can generate random numbers between 0.0 and 1.0, that you can use to inject randomness into your design.
Also, have a look at this http://osvvm.org/ It is a package of functions for constrained random generation with various distrubutions (including gaussian)- Als neu kennzeichnen
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PS. It is not for VHDL beginners though. Would make a good project (and you would learn a lot of the features of VHDL)
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I'm surprised Dave hasn't weighed in on this, he has written an excellent tutorial on the subject along with sample code;
http://www.ovro.caltech.edu/~dwh/cor...r_tutorial.pdf http://www.ovro.caltech.edu/~dwh/cor...torial_src.zip- Als neu kennzeichnen
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Ha! You beat me to it :)
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thanks,maybe i just simulate in matlab before
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--- Quote Start --- thanks,maybe i just simulate in matlab before --- Quote End --- The tutorial has MATLAB code as well as VHDL code. Cheers, Dave

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