how to get part of variable of type std_logic_vector like substring function

[Altera_Forum]

for example 

 temp : std_logic_vector[31 downto 0]   just want to get starting from 3th bit to 5th bit and store to another variable of type std_logic_vector[2 downto 0]  like offset  how to write in vhdl?

[Altera_Forum]

variable temp2 : std_logic_vector(2 downto 0); 

 ....  temp2 := temp(5 downto 3);

[Altera_Forum]

i mean temp2 : std_logic_vector(6 downto 0) := "011011" 

 if want to get from bit 3 to bit 5 which is 101  does it need to write a substring function or is there a function that can do this?

[Altera_Forum]

I dont quite understand what you mean. You can slice an array like I showed you. 

 temp3 := temp2(5 downto 3);