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SAbde7
Beginner
432 Views

how to reset registers in Verilog with minimal resource utilization.

I am using Quartus. I am programming an algorithm in which under certain conditions, certain values should be set to 0.

When I implement synchronous resets for these values, Quartus seems to implement multiplexers sometimes, and sometimes not. I am really trying to minimize resource usage and don't really understand why resets cost so much resources since the registers in the ALMS should have reset pins. What is the mechanic behind this? What should I do to minimize resource consumption?

 

 

I have tried the syntax :

-----------------------------

always @(posedge clock)begin

if(reset_condition)begin

value <=0;

end else begin

value <= comb_logic;

end

end

 

----------------------also

 

assign value_wire = reset_condition? 0:comb_logic;

always (@posedge clock)begin

value <= value_wire ;

end

----------------------

both ways sometimes increases ALUT usage and sometimes not but are not always equivalent. For example say I have 3x 15 bit variables in my design. At base none of them have resets. If I implement a [? ]reset or an [if else] reset on variable 1, it increases ALUT count by 15. If I implement a[?] reset on variable 2, it also increases ALUT count by 15, but if I use an [if-else] reset on that same variable instead, ALUT count doesnt increase. the third scenario is the opposite for variable 3 where [if else] increases ressources but [?] doesn't

 

also, would it be viable to & every bit of the input wire with ~(reset condition) to reduce resource consumption?

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5 Replies
MEIYAN_L_Intel
Employee
71 Views

Hi,

I had done the tests with one variable on the code u gave as above, I saw the resource utilization is same. May I have the test cases for three scenarios mentioned so that I can duplicate and investigate the differences.

Also, may i know which device used for the design?

Thanks.

SAbde7
Beginner
71 Views

I have already changed the code and am still testing how the new code behaves , so I have no test case to give at the moment. In the meantime I would like to know if resets are supposed to cost resources at all. I am using the DE5-net kit (Stratix V).

MEIYAN_L_Intel
Employee
71 Views

Hi,

The synchronous reset will cost the resources.

Also, I had found the ALM register ports information located at "ALM Resources" as the link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-v/stx5_core.pdf

Thanks.

SAbde7
Beginner
71 Views

But the link you provided states that the registers in the ALMs have synchronous clear inputs, so why would using these inputs increase resource count?

MEIYAN_L_Intel
Employee
71 Views

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