`timescale 1ns/1ps means that all the delays that follow (like# 5.1234) are interpreted to be in nanoseconds and any fractions will be rounded to the nearest picosecond (5123ps). However, all delays are represented as integers. The simulator knows nothing about seconds or nanoseconds, only unit-less integers.
It might help to understand that Verilog is defined with discrete event-driven simulation semantics. That means simulation time is defined as an integer, and all signal changes (events) scheduled for a later time are put into queues. A queue for a discrete time in the future is created as soon as an event needs to be scheduled for that time. As soon as all the events for the current time are finished, the simulator looks for the next time queue where an event is scheduled, advances the current time to that next time, and the process repeats until there is nothing left to do, or it executes a $finish. Time is discrete because the simulator only executes the times where events are scheduled, and skips over everything else.
In order to synchronize the scheduling of events across different modules with different timescales and precisions, the simulator picks the smallest time precision across used in the entire design and assigns that the value of 1 time unit integer. If the smallest precision was 10ps, that becomes the global value of 1 time unit. So if there were a module with a timescale of 1ns/1ns and there was a delay of# 12.3, that would be rounded to 12ns and then scaled to an integer of 1200. (1200x10ps= 12ns)
