if Clock 50MHz, how many ns used is appropriate for behavior vhdl ?

[Altera_Forum]

if Clock 50MHz, what is the maximum ns in after X ns can be used is appropriate for behavior vhdl ? 

 for example http://www.people.vcu.edu/~rhklenke/tutorials/vhdl/modules/m12_23/sld006.htm

[Altera_Forum]

None. After is not synthesisable, it is for behavioural modelling in simulation only. It is ignored for synthesis. 

 Why do you want a delay anyway? if you're trying to delay a signal to get something to work, the design is fundamentally wrong.

[Altera_Forum]

i do not know how long of my algorithm running in FPGA, so i afraid that i am not fast enough send data through ethernet before one clock cycle finish

[Altera_Forum]

But you know how long it will take - 1 clock cycle (though that seems rather short for "an algorithm"). So why do you need a delay? delays need to be in numbers of clocks, not fixed time delays. Digital circuits do not work like that.

[Altera_Forum]

once receive a message, i would like to send immediately while algorithm running at the same time

[Altera_Forum]

I dont quite understand. If you just want to send a reply in parrallel to the algorithm, why cant you just do that, and then send the data from the algorithm when it finishes?

[Altera_Forum]

because data are continously receive like a flow or stream and then algorithm and send. sending ethernet frame occupy many cycles, i wish to make algorithm involve in it. actually i do not know how many average cycles of an algorithm occupy in FPGA chip,  

if can not do algorithm within cycles of sending ethernet header before send a payload, there is only one choice that do it sequentially which is to finish algorithm first then send ethernet frame  is the clock cycle in ethernet frame 1/(50 * 10^6) = 0.00000002 = 20 ns ? if sending ethernet frame using 8 * 20ns, can an algorithm run within 8 * 20 ns?

[Altera_Forum]

Timings on ethernet do not matter - you just get a chunk of data. Your algorthm takes N clock to complete (N is probbably going to be a fixed length) and then you send the data back to the host.

[Altera_Forum]

how to know how many nanosecond of each VHDL statement? 

i would like to run algorithms partly using the rest of time in a cycle

[Altera_Forum]

you know the time, because of the clock speed. So an algorithm takes N (pipeline length) x clock period. Without a clock, you have no idea how "long" it will take.