.ip/.qip PLL how to disable sdc generation?

[AEsqu]

Hello,

When I create a PLL IP via Quartus (22.4 pro),

It also creates .sdc constraint for it which clashes with my .sdc constraint (duplicate point, not possible to set as async group ..).

I couldn't see an option in the GUI to turn it off while creating the PLL (stratix 10),

but I do see in the .ip that it has an option for that:

<ipxact:parameter parameterId="gui_skip_sdc_generation" type="bit">
<ipxact:name>gui_skip_sdc_generation</ipxact:name>
<ipxact:displayName></ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>

How to change it into true in the GUI to skip the sdc generation?

Can I otherwise comment out the sdc file pointer in the .qip to make sure it is not used in Quartus?

set_instance_assignment -entity "free_running_48mhz_pll_altera_iopll_1931_3tltc2i" -library "altera_iopll_1931" -name SDC_ENTITY_FILE [file join $::quartus(qip_path) "altera_iopll_1931/synth/free_running_48mhz_pll_altera_iopll_1931_3tltc2i.sdc"] -no_sdc_promotion -no_auto_inst_discovery

Note: When I remove the .sdc from the Quartus settings windows,

It removes the entire .qip line in the .qsf ...

Thanks,

Alex.
 

[AEsqu]

When I comment out the .sdc in the .qip, this is better, I do not get the duplicated clock points.

Side effect is that there is one point in each PLL that has no clock definition:

Info(13166): Register stratix10_fpga_a_mix_inst|PMU_TOP|pmu_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~pll_e_reg__nff is being clocked by stratix10_fpga_a_mix_inst|PMU_TOP|pmu_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg 
Info(13166): Register stratix10_fpga_a_mix_inst|PMU_TOP|free_running_48mhz_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~pll_e_reg__nff is being clocked by stratix10_fpga_a_mix_inst|PMU_TOP|free_running_48mhz_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg 
Info(13166): Register stratix10_fpga_a_mix_inst|PMU_TOP|flash_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~pll_e_reg__nff is being clocked by stratix10_fpga_a_mix_inst|PMU_TOP|flash_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg 
Info(13166): Latch stratix10_fpga_a_mix_inst|PMU_TOP|flash_48M_clk_enable is being clocked by stratix10_fpga_a_mix_inst|PMU_TOP|flash_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~c0cntr_reg 
Warning(332060): Node: stratix10_fpga_a_mix_inst|PMU_TOP|pmu_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg was determined to be a clock but was found without an associated clock assignment. 
	Info(13166): Register stratix10_fpga_a_mix_inst|PMU_TOP|pmu_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~pll_e_reg__nff is being clocked by stratix10_fpga_a_mix_inst|PMU_TOP|pmu_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg 
Warning(332060): Node: stratix10_fpga_a_mix_inst|PMU_TOP|free_running_48mhz_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg was determined to be a clock but was found without an associated clock assignment. 
	Info(13166): Register stratix10_fpga_a_mix_inst|PMU_TOP|free_running_48mhz_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~pll_e_reg__nff is being clocked by stratix10_fpga_a_mix_inst|PMU_TOP|free_running_48mhz_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg 
Warning(332060): Node: stratix10_fpga_a_mix_inst|PMU_TOP|flash_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg was determined to be a clock but was found without an associated clock assignment. 
	Info(13166): Register stratix10_fpga_a_mix_inst|PMU_TOP|flash_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~pll_e_reg__nff is being clocked by stratix10_fpga_a_mix_inst|PMU_TOP|flash_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg 
Warning(332060): Node: stratix10_fpga_a_mix_inst|PMU_TOP|flash_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~c0cntr_reg was determined to be a clock but was found without an associated clock assignment. 
	Info(13166): Latch stratix10_fpga_a_mix_inst|PMU_TOP|flash_48M_clk_enable is being clocked by stratix10_fpga_a_mix_inst|PMU_TOP|flash_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~c0cntr_reg 

 (s10_iopll.fourteennm_pll~c0cntr_reg) 

[RichardTanSY_Altera]

By default, you can't edit this parameter in the IOPLL IP as it is invisible, but you can do some script changes and make it visible in the GUI when you initialize the IP.

Find altera_iopll_init.tcl file in the <quartus installation directory>\ip\altera\altera_iopll\common, go to line 301 and changes it from:

{gui_skip_sdc_generation    BOOLEAN ""   ""    false   true false \

                  true          "" } \

to:

{gui_skip_sdc_generation    BOOLEAN ""   ""    true   true false \

                  true          "" } \

After that, open the iopll.ip parameter editor GUI, in your Quartus project navigator, and you can see Parameter tab and an option "gui_skip_sdc_generation" pop up. Click it to enable it.

Best Regards,

Richard Tan

[AEsqu]

Thank You for this info Richard but

as Quartus is installed centrally by our IT, I cannot change the option.

Would that be possible to make the option visible by default in a future version of Quartus?

Thanks.

Alex.

[RichardTanSY_Altera]

I can check with the engineering team to see if they are okay with making the changes.

Before I make the request, could you help provide justification for why you want to skip the SDC generation?

You may provide details on the specific problem or limitation you faced, the benefits of this feature, or any additional feedback that may help.

Best Regards,

Richard Tan

[AEsqu]

Thanks Richard.

I want to disable the SDC generation because I'm not able to make the different clock outputs of the PLL

asynchronous clock domain (due to the generated .sdc which define clock points in not async group).

I already do defined myself the PLL clock output and  the clock domains.

Alex.

[sstrell]

If you're trying to use set_clock_groups, can't you just add them to your top-level .sdc file which would override the PLL .sdc?

[RichardTanSY_Altera]

I have submitted an enhancement request to our engineering team.

Please be aware that implementing new features or enhancements for Quartus can be a time-consuming process. 

We appreciate your understanding and patience regarding this matter.

If you require any further assistance or have additional questions, please don't hesitate to let me know. 

Best Regards,

Richard Tan

[AEsqu]

Thank You very much Richard!

Will I get a notification when it is implemented?

Thanks.

[RichardTanSY_Altera · Accepted solution]

Unfortunately, we don't have a notification system in place. However, I can provide you with a ticket ID [15013771573] so that you can submit a new case and get an updates on this enhancement request status from the respective agent. This will allow you to inquire about the status of the request, whether it is planned, implemented, or rejected. I suggest requesting an update after approximately one year or so.

It's worth mentioning that there is a backlog of enhancement requests on the engineering side, and resources are limited. This is the reason for the extended timeframe required.

Thank you for your understanding.

Best Regards,

Richard Tan

[AEsqu]

ok.

[RichardTanSY_Altera]

Thank you for acknowledging the solution provided. I'm glad to hear that your question has been addressed. Now, I will transition this thread to community support.

If you have any further questions or concerns, please don't hesitate to reach out.

Thank you and have a great day!

Best Regards,

Richard Tan

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