load .mif-file on DE0-CV board

[Altera_Forum]

-- i solved the problems i had. to see the solution have a look at post# 9 -- 

  Hello community,  I got a problem with my mif file. I've never worked with that before but I want to change the default values in my memory. The mif-file is already created (two versions: one with text editor and one with memory editor) but I have no idea how to upload the file to my board.  I'm a beginner in working with vhdl and Quartus so my skills are limited :P I'm able to upload an output file with the programmer which is created after compiling. But I have no idea how to upload the mif file.  The board I'm using is a DE0-CV Cyclone V 5CEBA4F23C7N and I'm working with Quartus prime lite edition.  Hope anybody can help me with this.  Best,  orPoG

[Altera_Forum]

Hello  

orPog,  See thread below, I presented a problem and included the solution (with .zip files) "Default Cannot initialize 2D array of bytes from file (ram_init_file / $readmemh): Solved"  Good Luck, Johi

[Altera_Forum]

Hello Johi, 

 unfortunately I have no idea how your code works. I've never seen code like '$readmemh' before :/  I just want to initialize the memory on my board. But It starts with the problem: How to connect the mif-file with the other files to get an output file generated by compiling which I can upload on my board. I'm also not sure if I wrapped the memory file correctly to my main code. I've never done that before and have no idea how it works. I'll attach the code I got until now. Maybe you see a problem in the wrapping part (after the 'begin' of my architecture)?  Best,  orPoG

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

and this is my memory-code: 

LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; ENTITY MBDMemory IS PORT ( data : IN STD_LOGIC_VECTOR (5 DOWNTO 0); inclock : IN STD_LOGIC := '1'; outclock : IN STD_LOGIC ; rdaddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0); wraddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0); wren : IN STD_LOGIC := '0'; q : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) ); END MBDMemory; ARCHITECTURE SYN OF mbdmemory IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); BEGIN q <= sub_wire0(5 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( address_aclr_b => "NONE", address_reg_b => "CLOCK0", clock_enable_input_a => "BYPASS", clock_enable_input_b => "BYPASS", clock_enable_output_b => "BYPASS", intended_device_family => "Cyclone V", lpm_type => "altsyncram", numwords_a => 64, numwords_b => 64, operation_mode => "DUAL_PORT", outdata_aclr_b => "NONE", outdata_reg_b => "CLOCK1", power_up_uninitialized => "FALSE", read_during_write_mode_mixed_ports => "OLD_DATA", widthad_a => 6, widthad_b => 6, width_a => 6, width_b => 6, width_byteena_a => 1 ) PORT MAP ( address_a => wraddress, address_b => rdaddress, clock0 => inclock, clock1 => outclock, data_a => data, wren_a => wren, q_b => sub_wire0 ); END SYN;

[Altera_Forum]

--- Quote Start ---  Hello Johi,  unfortunately I have no idea how your code works. I've never seen code like '$readmemh' before :/  I just want to initialize the memory on my board. But It starts with the problem: How to connect the mif-file with the other files to get an output file generated by compiling which I can upload on my board. I'm also not sure if I wrapped the memory file correctly to my main code. I've never done that before and have no idea how it works. I'll attach the code I got until now. Maybe you see a problem in the wrapping part (after the 'begin' of my architecture)?  Best,  orPoG  --- Quote End ---    The trick is the .mif file (a text file icluded in your project) and refer to it in your declaration Then you compile the project and download it to your FPGA.  Examples: VHDL: type font_rom_type is array(0 to 255*16) of bit_vector(7 downto 0); signal font_rom : font_rom_type; attribute ram_init_file : string; attribute ram_init_file of font_rom : signal is "Bm437_IBM_VGA8.mif";  VERILOG: // Bitmap font: (* ram_init_file = "Bm437_IBM_VGA8.mif" *) reg [7:0] Bm437_IBM_VGA8[4096];  Best Regards, Johi.

[Altera_Forum]

Hello Johi, 

 thanks for your help! Unfortunately now the project doesn't even want to compile. I tried to write your code (of course modified) at different places but it didn't work. Here is the modified part of my code:  architecture behavior of MemoryBasedDesign is type mif_file_type is array(0 to 64*6) of bit_vector(5 downto 0); signal mif_file : mif_file_type; attribute mif_file_init_file : string; attribute mif_file_init_file of mif_file : signal is "mif_file.mif"; --VERILOG: --Bitmap font: (* mif_file_init_file = "mif_file.mif" *) reg mif_file; -- wrapper component MBDMemory port( data : IN STD_LOGIC_VECTOR (5 DOWNTO 0); inclock : IN STD_LOGIC := '1'; outclock : IN STD_LOGIC ; rdaddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0); wraddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0); wren : IN STD_LOGIC := '0'; q : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) ); end component;  Can you see where the problem is?  Best, orPoG

[Altera_Forum]

and here is my mif-file: 

 DEPTH = 64; % Memory depth and width are required % WIDTH = 6; % Enter a decimal number % ADDRESS_RADIX = HEX; % Address and value radixes are optional % DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % CONTENT BEGIN : 0000; % Range--Every address from 00 to 3F = 0000 % 00 : 0x22; 01 : 000011; 02 : 22; 03 : 0x22; 04 : 0x22; 05 : 0x22; END ;  I just want to change some of the memory blocks for testing reasons. Because I'm not sure how i write it correctly I tried different possibilities.   The memory is a 64 x 6-bit memory. So do I have to write  000001 or "000001" or 1 or '1' or 0x1 or "0x1" for e.g. a value of 1?

[Altera_Forum]

Okay, here a short update how I solved the problem if somebody got similar problems as I had. 

 1. to include the mif-file to the memory you need to create this one first and then create the memory. During the creationprocess of the memory with the Megawizard it's possible to include a Mif-file. On this way you get your memory with the desired values. The code for the Mif file is the following:  DEPTH = 64; % Memory depth and width are required %WIDTH = 6; % Enter a decimal number % ADDRESS_RADIX = HEX; % Address and value radixes are optional % DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % CONTENT BEGIN : 0000; % Range--Every address from 00 to FF = 0000 % 00 : 0; -- to get the value '0' to the memory location 0 01 : 1; -- to get the value '1' to the memory location 1 02 : A; -- to get the value '0xA' to the memory location 2 ... continue this way END ;  2. to wrap two vhdl-files together (in this case the memory file, created with the Megawizard, and the main file), you need to write the following code into the main vhdl file:  This part is placed directly after the 'architecture xx of yy is', before the 'begin'. (like the signals) -- wrapper component MBDDesignMemoryMif port( data : IN STD_LOGIC_VECTOR (5 DOWNTO 0); inclock : IN STD_LOGIC := '1'; outclock : IN STD_LOGIC ; rdaddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0); wraddress : IN STD_LOGIC_VECTOR (5 DOWNTO 0); wren : IN STD_LOGIC := '0'; q : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) ); end component;  This part is placed after the 'begin' of the architecture: uut: MBDDesignMemoryMif port map(data => WriteData, inclock => clock_10hz_int, outclock => clock_10hz_int, rdaddress => ReadAddress, wraddress => WriteAddress, wren => WriteEN, q => ReadData );  All the shown code parts in this post belong and work with the variables of my project, which I already posted in this thread.  Hopefully I can help somebody with this ;)