lookup table (LUT) in Verilog

[Altera_Forum]

I know there are many ways to implement a LUT on FPGA. I am trying to use case statement for this implementation because it is very easy. Basically, what I am trying to get is an one dimentional array. Then, the element value is stored in the corresponding place in the case statement. Could there be any problems with such a implementation? I simply couldn't get the design synthesized. Thanks.

[Altera_Forum]

Is it synchronous? have you followed the coding templates? 

how about posting the code so we can see whats wrong.

[Altera_Forum]

Where is the code templates? I have already posted the code, but I got errors. Please see my recent posted attachment

[Altera_Forum]

module lut(count_out, angle); 

input [2:0] count_out;  output [11:0] angle;  reg [11:0] angle;   always @(count_out)  case (count_out)  3'b000: angle=12'b001000000000; //0 45 45  3'b001: angle=12'b000100101110; //1 26.54 26.57  3'b010: angle=12'b000010100000; //2 14.06 14.036  3'b011: angle=12'b000001010001; //3 7.12 7.13  3'b100: angle=12'b000000101001; //4 3.604 3.576  3'b101: angle=12'b000000010100; //5 1.76 1.79  3'b110: angle=12'b000000001010; //6 0.88 0.9  3'b111: angle=12'b000000000101; //7 0.44 0.45  default: angle=12'b001000000000; //default 0  endcase  endmodule

[Altera_Forum]

The design has no errors.

[Altera_Forum]

Thank you very much