Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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manual placement of components

Altera_Forum
Honored Contributor II
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hello everyone, 

 

how can i implement manual placement of cells in Quartus9.0 web pack? 

like creating location constraints for some cells. 

 

thank you, 

randeel.
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Altera_Forum
Honored Contributor II
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They can be entered in the Assignment Editor or as tcl commands.

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Altera_Forum
Honored Contributor II
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hi, 

 

any reference document that describes this task? 

 

 

thank you, 

randeel.
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Altera_Forum
Honored Contributor II
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These procedures are basically discussed in quartus ii handbook version 9.0 volume 2: design implementation and optimization, particularly section iii. area, timing and power optimization.

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Altera_Forum
Honored Contributor II
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LogicLock regions is another option: 

 

Best Practices for Incremental Compilation Partitions and Floorplan Assignments 

 

http://www.altera.com/literature/hb/qts/qts_qii51017.pdf
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Altera_Forum
Honored Contributor II
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found it, 

 

set_location_assignment FF_X16_Y1_N31 -to "component_name" 

 

it is written to the qsf file. 

 

type of thing can be done 

 

http://www.altera.com/education/training/courses/odsw1155 

 

describes how to use chip planner to do Assignments 

 

thank you, 

randeel.
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Altera_Forum
Honored Contributor II
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Is there a chance to synthesize a script which generates placement contraints automatically from given demands? 

 

I have the task to create a certain structure which has to be organized in a kind a matrix in order to obtain the most possible clean routing delay characteristics between modules.:rolleyes:
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Is there a chance to synthesize a script which generates placement contraints automatically from given demands? 

 

I have the task to create a certain structure which has to be organized in a kind a matrix in order to obtain the most possible clean routing delay characteristics between modules.:rolleyes: 

--- Quote End ---  

 

 

Hi fpgaengineerfrankfurt, 

 

HAve you found a way which generates placement contraints automatically from given demands? I have the same issue. I need to fix the placement of modules in fpga 

 

Thanks
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