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I am using Quartus Prime Lite 15.1/modelsim-Altera starter 10.4 - university edition (professor)
When I create fixed ports in VHDL ... port (aa, bb: in STD_LOGIC_VECTOR(7 downto 0); ... then start modelsim and select "create wave", it finds all the ports and properly defines their widths and all is well If I replace the port definition with a generic ... generic( N: INTEGER := 8); port (aa, bb: in STD_LOGIC_VECTOR(N-1 downto 0); ... then start modelsim and select "create wave", it finds all the ports but defines any port using a generic as 1 bit wide - not allowing me to create proper waveforms In either case if I start a simulation, or add waves, the signals are the correct width as expected since the design properly analyzes and elaborates Summary: I can't "create wave" in modelsim if my ports use a generic to determine width and hence cannot generate input waveforms for ports w/generics Any ideas?Link Copied
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Without elaborating the design, modelsim has no way of knowing how wide the busses are.
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The design was properly elaborated - no errors or warnings. I've attached a screenshot of modelsim showing the incorrectly generated "create wave" signals AND the correctly generated simulation variables. Again - this works fine if I remove the Generic form the code and replace it with a constant.
https://www.alteraforum.com/forum/attachment.php?attachmentid=12332- Mark as New
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I have also attached the working version
https://www.alteraforum.com/forum/attachment.php?attachmentid=12333
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