Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,874 Views

modelsim Error: (vlog-13036) near "--": Operator only allowed in SystemVerilog.

Hi, 

 

After trying to simulate (with no success for now) Arria10 fifo with Quartus 18 Standard installation and modelsim altera starter edition in linux: https://www.alteraforum.com/forum/showthread.php?t=59117 

 

I've jumped to use Quartus 18 Pro edition with modelsim Intel FPGA Edition 10.6c. 

Despite the awful surprise that there is no more simple button for simulation, I've followed the Intel Simulation Quic-Start for Modelsim* - Intel FPGA Edition, and after some complications like " modelsim doesn't like '\' as folder separator(default in windows)" and other minor problems, I get to the error shown in the copy of the transcript I left here. I also add the code. 

 

Thanks, 

Guillermo 

 

MODELSIM TRANSCRIPT 

 

...# Model Technology ModelSim - Intel FPGA Edition vcom 10.6c Compiler 2017.07 Jul 26 2017# Start time: 19:29:03 on Jul 02,2018# vcom -reportprogress 300 D:/LHCb/Arria10Tests/fifoTest/fifo4fifoTest1/fifo_180/sim/fifo4fifoTest1_fifo_180_kjud6dq.vhd -work fifo_180 # -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Compiling entity fifo4fifoTest1_fifo_180_kjud6dq# -- Compiling architecture SYN of fifo4fifoTest1_fifo_180_kjud6dq# End time: 19:29:03 on Jul 02,2018, Elapsed time: 0:00:00# Errors: 0, Warnings: 0# Model Technology ModelSim - Intel FPGA Edition vcom 10.6c Compiler 2017.07 Jul 26 2017# Start time: 19:29:03 on Jul 02,2018# vcom -reportprogress 300 D:/LHCb/Arria10Tests/fifoTest/fifo4fifoTest1/sim/fifo4fifoTest1.vhd -work fifo4fifoTest1 # -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Loading package NUMERIC_STD# -- Compiling entity fifo4fifoTest1# -- Compiling architecture rtl of fifo4fifoTest1# -- Loading entity fifo4fifoTest1_fifo_180_kjud6dq# End time: 19:29:03 on Jul 02,2018, Elapsed time: 0:00:00# Errors: 0, Warnings: 0# Model Technology ModelSim - Intel FPGA Edition vlog 10.6c Compiler 2017.07 Jul 26 2017# Start time: 19:29:03 on Jul 02,2018# vlog -reportprogress 300 -work work D:/LHCb/Arria10Tests/fifoTest/fifoTest1TB.vhd # ** Error: (vlog-13036) D:/LHCb/Arria10Tests/fifoTest/fifoTest1TB.vhd(1): near "--": Operator only allowed in SystemVerilog.# ** Error: (vlog-13069) D:/LHCb/Arria10Tests/fifoTest/fifoTest1TB.vhd(1): near "--": syntax error, unexpected --, expecting class.# End time: 19:29:03 on Jul 02,2018, Elapsed time: 0:00:00# Errors: 2, Warnings: 0# ** Error: C:/intelFPGA_pro/18.0/modelsim_ae/win32aloem/vlog failed.# Error in macro ./msim_setup.do line 33# C:/intelFPGA_pro/18.0/modelsim_ae/win32aloem/vlog failed.# while executing# "vlog -work work D:/LHCb/Arria10Tests/fifoTest/fifoTest1TB.vhd"  

 

TESTBENCH 

 

--library ieee; --use ieee.std_logic_unsigned.all; --use ieee.std_logic_1164.all; --use ieee.std_logic_textio.all; --use ieee.numeric_std.all; -- --library STD; --use STD.textio.all; -- --library altera; --use altera.all; --use work.all; library ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std.all; entity testbench is end testbench; architecture behave of testbench is component Arria10FifoTest1 IS PORT( nReset : in std_logic; ClkIn : in std_logic; DataIn : in std_logic_vector(23 downto 0); DataInValid : in std_logic; ClkOut : in std_logic; DataOut : out std_logic_vector(23 downto 0) ); END component Arria10FifoTest1; signal nReset : std_logic := '0'; signal ClkIn : std_logic := '0'; signal ClkOut : std_logic := '0'; signal DataInValid : std_logic; signal DataIn : std_logic_vector(23 downto 0); signal DataOut : std_logic_vector(23 downto 0); constant PERIOD_ClkIn : time := 5 ns; constant PERIOD_ClkOut : time := 4 ns; begin tbu0 : component Arria10FifoTest1 port map( nReset => nReset, ClkIn => ClkIn, DataIn => DataIn, DataInValid => DataInValid, ClkOut => ClkOut, DataOut => DataOut ); genClkIn : process (ClkIn) begin ClkIn <= not ClkIn after PERIOD_ClkIn/2; end process; gen_clock_usb : process (ClkOut) begin ClkOut <= not ClkOut after PERIOD_ClkOut/2; end process; rst_gen: process begin nReset <= '0'; wait for PERIOD_ClkIn * 5; nReset <= '1'; wait; end process rst_gen; gen_aux_data : process begin DataIn <= (others => '0'); loop wait until (ClkIn'event and ClkIn = '0'); DataIn <= std_logic_vector(unsigned(DataIn) + 1); end loop; end process; end behave;  

 

TOP LEVEL 

 

LIBRARY ieee; USE ieee.std_logic_1164.all; --use IEEE.STD_LOGIC_1164.all; use IEEE.numeric_std.all; ENTITY Arria10FifoTest1 IS PORT( nReset : in std_logic; ClkIn : in std_logic; DataIn : in std_logic_vector(23 downto 0); DataInValid : in std_logic; ClkOut : in std_logic; DataOut : out std_logic_vector(23 downto 0) ); END Arria10FifoTest1; architecture beh of Arria10FifoTest1 is component fifo4fifoTest1 is port ( data : in std_logic_vector(23 downto 0) := (others => 'X'); -- datain wrreq : in std_logic := 'X'; -- wrreq rdreq : in std_logic := 'X'; -- rdreq wrclk : in std_logic := 'X'; -- wrclk rdclk : in std_logic := 'X'; -- rdclk aclr : in std_logic := 'X'; -- aclr q : out std_logic_vector(23 downto 0); -- dataout rdempty : out std_logic; -- rdempty wrfull : out std_logic -- wrfull ); end component fifo4fifoTest1; signal fifoRempty,fifoWfull : std_logic; signal fifoRreq,fifoWreq : std_logic; signal DataBuff : std_logic_vector(23 downto 0); begin u0 : component fifo4fifoTest1 port map ( data => DataIn, -- fifo_input.datain wrreq => fifoWreq, -- .wrreq rdreq => fifoRreq, -- .rdreq wrclk => ClkIn, -- .wrclk rdclk => ClkOut, -- .rdclk aclr => nReset, -- .aclr q => DataOut, -- fifo_output.dataout rdempty => fifoRempty, -- .rdempty wrfull => fifoWfull -- .wrfull ); fifoRreq <= '1'; fifoWreq <= DataInValid; -- inl : process(nReset,ClkIn) begin -- if ( nReset = '0') then -- DataBuff <= (others => '1'); -- elsif rising_edge(ClkIn) then -- DataBuff <= DataIn; -- end if; -- end process; -- -- outl : process(nReset,ClkOut) begin -- if ( nReset = '0') then -- DataOut <= (others => '1'); -- elsif rising_edge(ClkOut) then -- DataOut <= DataBuff; -- end if; -- end process; end beh;
0 Kudos
2 Replies
Altera_Forum
Honored Contributor I
705 Views

you're compiling a VHDL file using the verilog compiler (vlog). You need to use vcom to compile VHDL files.

Altera_Forum
Honored Contributor I
705 Views

Yes!! Thank you 

 

Also I had to change the file included to the one that was in the sim folder of the IP module
Reply