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Hi All,
I'm hoping someone can help with an issue I've observed in modelsim (10.5b, quartus 17.0). Simply put the clock network correctly drives the network right up to the point where it reaches the register at which point it stays stuck at 'StX'. I've traced the drivers and there is only one, I've re-written it to look like the Altera multi-tap shift register example, removed the reset, add default case. The dataflow diagram is attached. The code is a very simple shift loaded register:
module shiftRegister (
input in,
input clk,
input en,
output d_out
);
// Internal 11 groups of 2 bits
logic d_reg;
always @(posedge clk)
begin
if(en)
d_reg <= {d_reg,in};
else
d_reg <= d_reg;
end // always
// sneaky cast ;-)
assign d_out = d_reg;
endmodule
The testbench is just reads a test vector:
// Test bench for shiftRegister.sv
//
// test_vector.txt (bb_b_b <in>_<en>)
timeunit 1ns/100ps;
module shiftRegister_tb;
// Glue for the instance
logic in;
logic clk;
logic en;
logic d_out;
// Internal, needed by testbench
integer tst_vec;
logic t;
always# 1 clk = ~clk;
initial begin
tst_vec = $fopen("../../test_vector.txt","r");
// just be clean and set an initial value.
clk = 1;
en = 0;
in = '0;
t = '0;
end
always @(posedge clk) begin
// Start looping the test vector to generate our input
if(!$feof(tst_vec)) begin
$fscanf(tst_vec,"%b",t);
in = t;
en = t;
end
else // when done just go quiet...
begin
en = 0;
in = '0;
end
end
shiftRegister dut (
.in(in),
.clk(clk),
.en(en),
.d_out(d_out)
);
endmodule
And the test vector is
00_0
00_0
00_0
00_0
00_0
01_0
10_0
00_0
00_0
11_1
10_1
01_1
00_1
11_1
10_1
01_1
00_1
11_1
10_1
01_1
00_0
00_0
00_0
I've reached a dead end in figuring this out, if anyone has any ideas please let me know. Thanks, -- Paul https://alteraforum.com/forum/attachment.php?attachmentid=14497&stc=1
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6 Replies
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I will initialise d_reg to known value to keep modelsim happy
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--- Quote Start --- I will initialise d_reg to known value to keep modelsim happy --- Quote End --- Hi, Original code (before I stripped it down to bare minimum) had a sync reset for d_reg and still exhibited the same behavior. Added initial power on state ("= '0;") and it still did the same thing. In all three cases (reset, power on state, and the above code) the simulator shows the register output settling to '0' within a few ns of the simulation. I forgot to mention that the RTL simulation works as expected. Even if I totally stuffed up timing closure I'd still expect the clock to the driven... Any other ideas? -- Paul
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Hi,
I just simulated the code you posted. I did parse the code through Quartus and generate the netlist via the Netlist writer. The gate-sim works fine. I don't see any issues.https://alteraforum.com/forum/attachment.php?attachmentid=14499&stc=1- Mark as New
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Thanks,
Could you let me know which version of quartus and which device you used? Given that it does actually work my issue is either human error (yes, I hate to admit it!) or device/tool specific. Regards, -- Paul- Mark as New
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Well, I did target the Cyclone V series as this is the Lite version of Quartus II 17.1 (Windows) that I'm using, ModelSim is the Intel starter version.
I did modify the testbench a little, nothing major.
// Test bench for shiftRegister.sv
//
// test_vector.txt (bb_b_b <in>_<en>)
timeunit 1ns/100ps;
module shiftRegister_tb;
// Glue for the instance
logic in;
logic clk;
logic en;
logic d_out;
// Internal, needed by testbench
integer tst_vec;
integer scan_file;
logic t;
always# 1 clk = ~clk;
initial begin
tst_vec = $fopen("test_vector.txt","r");
// just be clean and set an initial value.
clk = 1;
en = 0;
in = '0;
t = '0;
end
always @(posedge clk) begin
// Start looping the test vector to generate our input
if(!$feof(tst_vec)) begin
scan_file = $fscanf(tst_vec,"%b",t);
in = t;
en = t;
end
else // when done just go quiet...
begin
en = 0;
in = '0;
$finish;
$fclose(tst_vec);
end
end
shiftReg dut (
.in(in),
.clk(clk),
.en(en),
.d_out(d_out)
);
endmodule
I had to change the name of the DUT as I didn't want it to overwrite the RTL simulation database. I've uploaded the netlist also. Have a look at it. The shiftReg.v file is the gate netlist. The other two are the design and TB files.
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Update.
Changed the device to a random arria v part and it worked. Stratix IV GX and E both failed with the same issue, I'm pretty sure all other stratic iv parts will exhibit the same issue. Thanks for your time in validating. -- Paul --- Quote Start --- Thanks, Could you let me know which version of quartus and which device you used? Given that it does actually work my issue is either human error (yes, I hate to admit it!) or device/tool specific. Regards, -- Paul --- Quote End ---
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