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I need to generate a constant high signal to output to an oscilloscope.
I tried letting the an signal pulse_out <='1' and this didn't work either. I believe due to my knowledge that an output port signal needs to be driven by a clock. I also tried using combinational logic and letting a two signals that were opposite of each other make a new signal by using AND,OR and this did not work either. I feel like this is alot simpler than I think it is but I've tried everything!!! Any sample code of showing how to output a constant high value of '1' would be great.Link Copied
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use assign statement: http://www.asic-world.com/verilog/synthesis3.html
this isn't clocked in an always block. Thus: assign output = 1'b1;- Mark as New
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--- Quote Start --- use assign statement: http://www.asic-world.com/verilog/synthesis3.html this isn't clocked in an always block. Thus: assign output = 1'b1; --- Quote End --- The op is asking for vhdl, not verilog. To the op. Assigning something to'1' should work just fine. You don't need a clock. What board are you using. Are you sure its not a problem of where you are probing?
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Is the pulse_out signal assigned to the correct device pin? I mean the one where your probe is connected.
Has the fpga properly configured?- Mark as New
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Solved. The oscilloscope that was used to detect the signal had a broken port.
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