pin placement error after upgrade from 18.0 pro to 21.2 pro

[AThom47]

Hi,

I have an Arria10 design that compiles fine in quartus 18.0 pro but throws the following error after upgrading to quartus 21.2 pro:

"Error (175020): The Fitter cannot place logic pin in region (78, 142) to (78, 143), to which it is constrained, because there are no valid locations in the region for logic of this type."

This is the reference clock pin for the HPS EMIF.

Some research pointed me to a possible solution of adding the following to the general section of the quartus2.ini file:

"EMIF_RESTRICT_HPS_REFCLK_TO_AC_TILE = off"

My quartus2.ini file didn't have a General section for 21.2 so I created one and the file now looks like this:

[General 17.1]
HDL_PREFERENCE = VHDL
IPGEN_INCLUDE_SIMULATION_FILESET = off
MANAGED_FLOW_HDL_PREFERENCE = VHDL
MAX_QSYS_JVM_MEMORY = Default

[General 18.0_pro]
HDL_PREFERENCE = Verilog
IPGEN_INCLUDE_SIMULATION_FILESET = off
MANAGED_FLOW_HDL_PREFERENCE = Verilog
MAX_QSYS_JVM_MEMORY = Default

[General 21.2_pro]
EMIF_RESTRICT_HPS_REFCLK_TO_AC_TILE = off

[Programmer 18.0_pro]
PGMDQ_INTERNAL_SETTING = 0
PGMW_SFL_USE_CRC_CHECK = on

When re-compiling I still get the same error though. Is there something else I need to do? How can I resolve this issue?

Thank you for your help.

[sstrell]

You shouldn't need an .ini file for Quartus unless you are enabling beta or other non-standard features.

Did you upgrade all the IP through regeneration of your Platform Designer system, including the HPS?  Check to make sure that all your IP (Platform Designer and otherwise) are up to the latest version.

[AThom47]

Yes, I have updated all IPs through the auto upgrade process with no errors, the versions are all updated from 18.0 to a mix of 19.1, 19.1.0 , 19.2.0, 19.2.2, 19.3.1 and 20.0.0

However I am still getting the following error:

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic pin in region (78, 142) to (78, 143), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): EMIF_REF_CLK
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (175005): Could not find a location with: HPS_IOPLL_REFCLK_PIN (1 location affected)
Info (175029): AL27
Info (175015): The I/O pad EMIF_REF_CLK is constrained to the location PIN_AL27 due to: User Location Constraints (PIN_AL27) File: C:/xyz/source/xyz/xyz.vhd Line: 113
Info (14709): The constrained I/O pad is contained within this pin
Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error (16297): An error has occurred while trying to initialize the plan stage.

As mentioned above I found other people having the same issue but in different quartus versions. I tried their solutions but they did not help. For reference the other posts about this that I found are here:

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Fitter-Error-with-Quartus-19-4-and-not-Quartus-19-1-for-HPS/m-p/595633/highlight/true

and

https://community.intel.com/t5/Programmable-Devices/clk-pll-input-location-for-DDR4-HPS-arria10sx066f34I2SG/m-p/728838

Any help on how I can fix the issue so I can build with quartus 21.2 is appreciated.

Thanks!

[AnilErinch_A_Intel]

Hi ,

Can you verify that the options which is provided in the IP is correct and similar to the one given in the older Quartus version before the IP update. You can also have a look at the below article.

https://www.intel.com/content/www/us/en/support/programmable/articles/000076453.html

Thanks and Regards

Anil

[AThom47]

Hi,

The link you provided talks about the mem_alert_n pin however as you can see from the error message I posted I am having issues with the reference clock input pin of the EMIF IP. 

The EMIF is part of a bigger platform designer system within our design.

I am not sure how to determine exactly what you are asking, however attached are the EMIF *.ip files from before and after the IP upgrade in the new tool (before_emif.ip is the ip file from the older 18.0.1 quartus version and after_emif.ip is from the 2021.2 quartus tool after having done the auto ip upgrade).

Can you tell from this if there is an issue? I am still trying to run the design in the new tool but can't because of the error I am getting.

Thanks!

[AnilErinch_A_Intel]

Hi ,

Can you also share the quartus.ini also in both the working and non working cases to get a better picture for debugging.

Thanks and Regards

Anil

[AThom47]

Hi Anil,

I am not sure exactly what you mean. There is a quartus2.ini located at c:/Users/Username that file is used for all versions if I understand correctly so there is not a separate ini file for the working version (18.0.1 Build 261 06/28/2018 SJ Pro Edition) vs. the not working version (21.2.0 Build 7206/14/2021 SC Pro Edition). I have both quartus version installed on one PC that is running windows 10.

I attached this ini file. Please note that I manually added line 14 and 15:

[General 21.2_pro]
EMIF_RESTRICT_HPS_REFCLK_TO_AC_TILE = off

Following the advise from this forum post: https://community.intel.com/t5/Intel-Quartus-Prime-Software/Fitter-Error-with-Quartus-19-4-and-not-Quartus-19-1-for-HPS/m-p/595633/highlight/true but it did not help or change anything. It still works with the 18 version and still doesn't with the 21 version.

Please let me know if you are looking for another file or if this is the one you were interested in.

Thanks!

[AnilErinch_A_Intel]

Hi Andre,

You can create a quartus.ini file and add the content to it.

Please see the below links on creation of ini file and using the same to change IP parameters.

https://www.macnica.co.jp/business/semiconductor/support/faqs/intel/130917/

https://www.intel.com/content/dam/www/programmable/us/en/kdb/fb470823/A10-PLL-Cascading-or-Non_dedicated-Clock-Path-Workaround-Guideline-for-Altera-PHYLite-IP_Rev1.pdf

Please let us know the feedback.

Thanks and Regards

Anil