Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

(vcom-1576) expecting ')'

Hieu007
Beginner
845 Views

Hey all, 

I've googled this problem and it always seems to be a missing semicolon or paren somewhere, but I've looked over my code and I see nothing. I know it's going to be simple and I will feel stupid, but I am just learning VHDL and going by the book. What is wrong with my signal declaration here? 

** Error: D:/tkhts2/hieu007.vhd(15): near "orsum": (vcom-1576) expecting ')'.

 

LIBRARY ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity BCD_Adder is
Port (
x,y :in std_logic_vector(3 downto 0);
S :out std_logic_vector(4 downto 0)
);
End BCD_Adder;
architecture Behavioral of BCD_Adder is
Signal adjust :std_logic;
Signal sum :std_logic_vector ( 4 downto 0);
begin
Sum <= ('0' & x)+y;
Adjust<='1'when((sum > 9) orsum(4)='l') else '0';
S <= sum when (adjust ='0') else Sum + 6;
end Behavioral;

0 Kudos
3 Replies
sstrell
Honored Contributor III
807 Views

There should be a space between "or" and "sum".

BoonBengT_Intel
Moderator
752 Views

Hi @Hieu007,

 

Thank you for posting in Intel community forum and hope all is well.
By any chances did you managed to look into the previous suggestion?
Please do let us know if there is further doubts.

 

Best Wishes
BB

BoonBengT_Intel
Moderator
650 Views

Hi @Hieu007,

 

Greetings, as we do not receive any further clarification on what is provided, we would assume challenge are resolved. Hence thread will no longer monitor this thread. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.

 

Best Wishes
BB

Reply