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preserve logic or insert internal buffer

OrF
従業員
1,842件の閲覧回数

Hi 

is there any attribute to keep 2 consecutive  NOT gate  in  synthesis ? some kind of preserve attribute , what I have found is preserving registers but logic gate (LUT)

OR 

other option is there away to push a "Internal" Buffer which will be kept in the synthesis process ?

 

Thanks

Or.

 

 

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1 解決策
Nurina
従業員
1,787件の閲覧回数

Hi Or,


Do the above comments help?


Regards,

Nurina


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5 返答(返信)
roeekalinsky
高評価コントリビューター I
1,829件の閲覧回数

Hi Or,

 

You can set the "keep" attribute on the signals that are the outputs of the inversions to prevent Quartus from optimizing them away.  See:

 

VHDL:
https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vhdl/vhdl_file_dir.htm

 

Verilog:
https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vlog/vlog_file_dir.htm

 

BTW, I'm not sure why you'd want to do this. If you're trying to cascade inverters to create a delay chain, then there's almost certainly a better way to go about whatever it is you're ultimately trying to accomplish.

 

Cheers,

-Roee

 

OrF
従業員
1,824件の閲覧回数

Hi Roee,

thanks for the fast response  , 

I DO want to cascade inverters to create delay chain - since we are trying to build a-sync design. 

any better way to create delay between logic cells ? 

Thanks

Or. 

roeekalinsky
高評価コントリビューター I
1,819件の閲覧回数

Hi Or,

I don't have any better suggestion for you toward that intent.

My broader advice would be to stick to synchronous design unless you have a very good reason to go async, and there is almost never a good reason to go async.  Especially in an FPGA.

But there are rare exceptions.  If you do have a good reason for going async, good luck!  You're living on the edge ; -)

-Roee

 

sstrell
名誉コントリビューター III
1,804件の閲覧回数

Yeah, relying on delay like that is really not recommended.  Just synch to a clock domain.  Add a counter if the delay needs to be more than a single clock cycle.

Nurina
従業員
1,788件の閲覧回数

Hi Or,


Do the above comments help?


Regards,

Nurina


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