problem whit component editor

[Altera_Forum]

hi!  

 i have problam whit next error: avalon_slave_0: Slave whit readdatavalid signal must support at least 1 pending read. i already try some instruction which are on the web and none of them didn't work.   this is my created component https://www.alteraforum.com/forum/attachment.php?attachmentid=6326   thanks for all answers good day

[Altera_Forum]

In the "Interfaces" tab, go to your avalon_slave_0 interface and look for the "Pipelined transfers" part. There replace the 0 in "Maximum pending read transactions" with the highest number of transactions you can hold in your pipeline.

[UserID4331231]

I have same error on Quartus 25.1 

Error: pcie_ed.custom_cntrlr_0.avalon_slave: Agent with readdatavalid signal must support at least 1 pending read.

as per https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/interface-properties.html

I tried setting "maximumPendingReadTransactions "  parameter by platform designer > IP> Edit IP> Parameters> add parameter

it didnt work and I cant generate HDL due to this error Pls help

[sstrell]

Probably would be better to create a new thread instead of reopening one from 13 years ago.

In any case, how are you coding the signal in your custom component?  And you must be using pipelined transfers with variable latency: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/pipelined-read-transfer-with-variable.html

[UserID4331231]

I did create new thread.

I haven't really started coding yet, just using assign statements so at least signals are not left open.   , I am exploring how to create a custom component /IP.