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This is my code, but I still need to generate the output on the displays.
Someone who can support me.
Thank you very much.
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.numeric_std.all;
Entity calc is
generic(constant n: natural := 1 );
Port (
a, b: in std_logic_vector (7 downto 0);
operacion: in std_logic_vector (4 downto 0);
resultado: out std_logic_vector (7 downto 0);
c: out std_logic
);
End calc;
Architecture arq of calc is
Signal tres: std_logic_vector(7 downto 0);
Signal tmp: std_logic_vector(8 downto 0);
begin
process (a,b,operacion)
begin
case(operacion) is
when "00000" => tres <= a+b;-- suma
when "00001"=> tres <= a-b; -- resta
when "00011" => tres <= std_logic_vector(to_unsigned(to_integer(unsigned(a)) * to_integer (unsigned(b)), 8));--multiplicación
when "00010" => tres <= std_logic_vector(to_unsigned(to_integer(unsigned(a)) / to_integer (unsigned(b)), 8));--división
when others => tres <= a+b;
end case;
end process;
resultado <= tres;
tmp<=('0' & a) + ('0' & b);
c <= tmp(8);
end arq;
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I don't think you're going to see folks here writing code for you.
For a seven-segment display, you need to write an encoder, usually a case statement (in a clocked process) or a selected signal assignment using WITH and SELECT (in a concurrent, non-clocked signal assignment), that enables the particular LED segments depending on the number you want to display.
Try writing the code and post it here for folks to check.
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Hi Javier,
I found an example related to Implementation of a 4-bit Adder with
7-segment HDL decoder using VHDL in the link below. Probably can give you some ideas. Most of time, decoder is used for seven segment display and in case you work with VHDL, you can use the "WITH-SELECT-WHEN".
http://www.pldworld.com/_hdl/2/-seas.upenn.edu/_ese201/lab/Lab4bAddDec/Lab4bAddDecF01.html
Thanks,
Regards
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Hi Javier,
Any update from your side?
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