quartus 2: can't determine definition of operator "*"

Altera_Forum · ‎02-24-2016

I've got this error for the following code:

library IEEE;

--use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

use IEEE.STD_LOGIC_TEXTIO.ALL;

use ieee.numeric_std.all;

--package image_array_2 is

-- type image_array is array(0 to 49, 0 to 49) of unsigned(7 downto 0);

--type image_derivadas is array(0 to 49, 0 to 49) of unsigned (8 downto 0);

--end package image_array_2;

use work.imagens.all;

entity hornteste is

Port (

clk : in bit;

imagem: in image_array;

imagemanterior: in image_array;

Ix: out image_derivadas;

Iy: out image_derivadas;

It: out image_derivadas

);

end hornteste;

architecture Behavioral of hornteste is

begin

process (clk)

begin

If (clk 'event and clk = '1') then

for x in imagem'range(1) loop

for y in imagem'range(2) loop

Ix(x,y) <= 1/4 * (imagemanterior(x,y+1) - imagemanterior(x,y) + imagemanterior (x+1,y+1) - imagemanterior(x+1,y) + imagem(x,y+1) - imagem(x,y)+imagem(x+1,y+1)-imagem(x,y+1));

Iy(x,y) <= 1/4*(imagemanterior(x+1,y) - imagemanterior(x,y) + imagemanterior(x+1,y+1) - imagemanterior(x,y+1) + imagem(x+1,y) - imagem(x,y) + imagem(x+1,y+1) -imagem(x,y+1));

It(x,y) <= 1/4 * (imagem(x,y) - imagemanterior(x,y) + imagem(x+1,y)- imagemanterior(x+1,y) +imagem(x,y+1)- imagemanterior(x,y+1) + imagem(x+1,y+1)- imagemanterior(x+1,y+1));

end loop;

end if ;

end process;

end Behavioral;

I've used the unsigned type for the signals in opertation. what's wrong with it? thanks in advance.

Altera_Forum · ‎02-24-2016

I cant see the package that contains the image_derivadas type. Have you accidently used std_logic_arith instead of numeric_std?

Just to note - all the Ix, Iy and It outputs are going to be 0 because 1/4 = 0

Altera_Forum · ‎02-24-2016

--- Quote Start ---

I cant see the package that contains the image_derivadas type. Have you accidently used std_logic_arith instead of numeric_std?

Just to note - all the Ix, Iy and It outputs are going to be 0 because 1/4 = 0

--- Quote End ---

the package is defined in another file as folowing:

package imagens is

type image_array is array(0 to 49, 0 to 49) of unsigned(7 downto 0);

type image_derivadas is array(0 to 49, 0 to 49) of signed (8 downto 0);

type image_19bits is array (0 to 49, 0 to 49) of signed (18 downto 0);

end imagens;

I've already had that kind of problem with divisions. Which is the best way to do a division in vhdl?

thanks.

Altera_Forum · ‎02-25-2016

Remember that 1/4 = 0 because it is integer division, and the VHDL rules mean that division is completed before multiply unless you put expressions in brackets. This is just standard programming when it comes to integer division

So 1/4 * 100 = 0

100 / 4 = 25.

Just put the /4 after the multiply:

(imagemanterior(x,y+1) - imagemanterior(x,y) + imagemanterior (x+1,y+1) - imagemanterior(x+1,y) + imagem(x,y+1) - imagem(x,y)+imagem(x+1,y+1)-imagem(x,y+1)) /4

/4 is safe in this case as it is just a power of 2, which is really just a bit shift and free in terms of logic. If you need any non-power of 2 division, then you need to use the division IP core.

The problem is because you are mixing signed and unsigned. Make everything signed and it should work.

Altera_Forum · ‎03-02-2016

--- Quote Start ---

Remember that 1/4 = 0 because it is integer division, and the VHDL rules mean that division is completed before multiply unless you put expressions in brackets. This is just standard programming when it comes to integer division

So 1/4 * 100 = 0

100 / 4 = 25.

Just put the /4 after the multiply:

(imagemanterior(x,y+1) - imagemanterior(x,y) + imagemanterior (x+1,y+1) - imagemanterior(x+1,y) + imagem(x,y+1) - imagem(x,y)+imagem(x+1,y+1)-imagem(x,y+1)) /4

/4 is safe in this case as it is just a power of 2, which is really just a bit shift and free in terms of logic. If you need any non-power of 2 division, then you need to use the division IP core.

The problem is because you are mixing signed and unsigned. Make everything signed and it should work.

--- Quote End ---

I've changed all to signed. I still get an error at definition of operator "-".

Altera_Forum · ‎03-02-2016

I get the feeling the problem you're having problems with code you havent posted here.

I have compiled your code in your original post without errors.

Please post the whole code.

Altera_Forum · ‎03-23-2016

--- Quote Start ---

I get the feeling the problem you're having problems with code you havent posted here.

I have compiled your code in your original post without errors.

Please post the whole code.

--- Quote End ---

the main code used in the project is called hornschunk and it was written like this:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_signed.ALL;

use IEEE.STD_LOGIC_TEXTIO.ALL;

use ieee.numeric_std.all;

package imagens is

type image_array is array(0 to 49, 0 to 49) of signed(8 downto 0);

type image_derivadas is array(0 to 49, 0 to 49) of signed (9 downto 0);

type image_19bits is array (0 to 49, 0 to 49) of signed (18 downto 0);

end imagens;

use work.imagens.all;

--type image_array is array(0 to 49, 0 to 49) of unsigned(7 downto 0);

entity opticalflow is

Port ( clk_0 : in bit;

ukfinal : out image_19bits ;

vkfinal: out image_19bits

);

end opticalflow;

architecture Behavioral of opticalflow is

signal entrada, entradaanterior : image_array;

signal Ix_0,Iy_0,It_0, dividendo_0 : image_derivadas;

signal divisor_0, uk_0, vk_0: image_19bits;

signal mediau_0, mediav_0, uk2_0, vk2_0,uk3_0,vk3_0, mediau2_0,mediav2_0,dividendo2_0,dividendo3_0: image_19bits;

--signal uk_0,vk_0,uk_1,vk_1,divisor_0 : SIGNED (32499 downto 0) ;

component inicializacao port(

clk: in bit;

imagem: out image_array;

imagemanterior: out image_array

); end component;

--*component inicializacao port(

-- clk: in bit;

-- imagem: out SIGNED (19999 DOWNTO 0);

-- imagemanterior: out SIGNED (19999 DOWNTO 0)

-- ); end component;

-- */

component stage_1 port(

clk: in bit ;

imagem : in image_array;

imagemanterior: in image_array;

Ix: out image_derivadas;

Iy : out image_derivadas;

It : out image_derivadas

); end component;

--component stage_1 port(

-- clk: in bit ;

-- imagem: in SIGNED (19999 DOWNTO 0);

-- imagemanterior: in SIGNED (19999 DOWNTO 0);

-- Ix: out SIGNED (3 DOWNTO 0);

-- Iy : out SIGNED (3 DOwNTO 0);

-- It : out SIGNED (3 DOWNTO 0)

-- ); end component;

component stage_2

port(

clk: in bit;

Ix: in image_derivadas;

Iy: in image_derivadas;

It: in image_derivadas;

divisor: out image_19bits;

dividendo: out image_derivadas

--uk:out SIGNED (9999 DOWnTO 0);

--vk:out SIGNED (9999 DOWNto 0)

); end component;

component first_iteration

port(

clk : in bit;

divisor: in image_19bits;

dividendo: in image_derivadas;

Ix: in image_derivadas;

Iy: in image_derivadas;

--uk: in SIGNED (9999 DOWNTO 0);

--vk: in SIGNED (9999 DOWNTO 0);

uk1: out image_19bits;

vk1: out image_19bits

); end component;

component medias_1

port(

clk: in bit;

uk1: in image_19bits;

vk1: in image_19bits;

mediau: out image_19bits;

mediav: out image_19bits

); end component;

component second_stage_2

port(

clk: in bit;

Ix: in image_derivadas;

Iy: in image_derivadas;

It: in image_derivadas;

mediau: in image_19bits;

mediav: in image_19bits;

dividendo2: out image_19bits

); end component;

component second_iteration

port(

clk: in bit;

divisor: in image_19bits;

dividendo2: in image_19bits;

mediau: in image_19bits;

mediav: in image_19bits;

Ix: in image_derivadas;

Iy: in image_derivadas;

uk2: out image_19bits;

vk2: out image_19bits

); end component;

component medias_2

port(

clk: in bit;

uk2: in image_19bits;

vk2: in image_19bits;

mediau2: out image_19bits;

mediav2: out image_19bits

); end component;

component third_stage_2

port(

clk: in bit;

Ix: in image_derivadas;

Iy: in image_derivadas;

It: in image_derivadas;

mediau2: in image_19bits;

mediav2: in image_19bits;

dividendo3: out image_19bits

); end component;

component third_iteration

port(

clk: in bit;

divisor: in image_19bits;

dividendo3: in image_19bits;

mediau2: in image_19bits;

mediav2: in image_19bits;

Ix: in image_derivadas;

Iy: in image_derivadas;

uk3: out image_19bits;

vk3: out image_19bits

); end component;

begin

U1: inicializacao PORT MAP (

clk=> clk_0,

imagem=> entrada,

imagemanterior => entradaanterior

);

U2: stage_1 PORT MAP (

clk => clk_0,

imagem =>entrada,

imagemanterior => entradaanterior,

Ix=> Ix_0,

Iy=>IY_0,

It=>IT_0

);

U3: stage_2 PORT MAP (

clk => clk_0,

Ix =>Ix_0,

Iy =>Iy_0,

It => It_0,

divisor => divisor_0,

dividendo => dividendo_0

);

U4: first_iteration PORT MAP (

clk => clk_0,

divisor => divisor_0,

dividendo => dividendo_0,

Ix => Ix_0,

Iy=> Iy_0,

uk1 => uk_0,

vk1 => vk_0

--uk1 => ukfinal,

--vk1 => vkfinal

);

U5: medias_1 PORT MAP(

clk => clk_0,

uk1 => uk_0,

vk1 => vk_0,

mediau => mediau_0,

mediav =>mediav_0

);

U6: second_stage_2 PORT MAP(

clk => clk_0,

Ix => Ix_0,

Iy => Iy_0,

It => It_0,

mediau => mediau_0,

mediav => mediav_0,

divdendo2 => dividendo2_0

);

U7: second_iteration PORT MAP(

clk => clk_0,

divisor => divisor_0,

dividendo2 => dividendo2_0,

mediau => mediau_0,

mediav => mediav_0,

Ix => Ix_0,

Iy => Iy_0,

uk2 => uk2_0,

vk2 => vk2_0

);

U8: medias_2 PORT MAP(

clk => clk_0,

uk2 => uk2_0,

vk2 => vk2_0,

mediau2 => mediau2_0,

mediav2 =>mediav2_0

);

U9: second_stage_2 PORT MAP(

clk => clk_0,

Ix => Ix_0,

Iy => Iy_0,

It => It_0,

mediau2 => mediau2_0,

mediav2 => mediav2_0,

divdendo2 => dividendo3_0

);

U10: third_iteration PORT MAP(

clk => clk_0,

divisor => divisor_0,

dividendo3 => dividendo3_0,

mediau2 => mediau2_0,

mediav2 => mediav2_0,

Ix => Ix_0,

Iy => Iy_0,

uk3 => uk3_0,

vk3 => vk3_0

);

end behavioral;

Altera_Forum · ‎03-23-2016

The problem with this code is nothing more than misnaming of signals

mediau2 should be mediau

divdendo2 should be dividendo2

Please review the errors and study your own code.

Altera_Forum · ‎03-23-2016

--- Quote Start ---

The problem with this code is nothing more than misnaming of signals

mediau2 should be mediau

divdendo2 should be dividendo2

Please review the errors and study your own code.

--- Quote End ---

thanks. but i still get an error at opertator "-" in the first code.

Altera_Forum · ‎03-24-2016

The problem you are having is not in the code in the first post - that code compiles fine (with some length missmatch warnings).

Please post the code you are working with now as it is clearly not the code in the first post.

Altera_Forum · ‎03-24-2016

--- Quote Start ---

The problem you are having is not in the code in the first post - that code compiles fine (with some length missmatch warnings).

Please post the code you are working with now as it is clearly not the code in the first post.

--- Quote End ---

the code is this:

library IEEE;

--use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_signed.ALL;

use IEEE.STD_LOGIC_TEXTIO.ALL;

--use ieee.numeric_std.all;

--package image_array_2 is

-- type image_array is array(0 to 49, 0 to 49) of unsigned(7 downto 0);

--type image_derivadas is array(0 to 49, 0 to 49) of unsigned (8 downto 0);

--end package image_array_2;

use work.imagens.all;

entity stage_1 is

Port (

clk : in bit;

imagem: in image_array;

imagemanterior: in image_array;

Ix: out image_derivadas;

Iy: out image_derivadas;

It: out image_derivadas

);

end stage_1;

architecture Behavioral of stage_1 is

begin

process (clk)

begin

If (clk 'event and clk = '1') then

for x in imagem'range(1) loop

for y in imagem'range(2) loop

Ix(x,y) <= ((imagemanterior(x,y+1) - imagemanterior(x,y) + imagemanterior (x+1,y+1) - imagemanterior(x+1,y) + imagem(x,y+1) - imagem(x,y)+imagem(x+1,y+1)-imagem(x,y+1)))/4;

Iy(x,y) <= ((imagemanterior(x+1,y) - imagemanterior(x,y) + imagemanterior(x+1,y+1) - imagemanterior(x,y+1) + imagem(x+1,y) - imagem(x,y) + imagem(x+1,y+1) -imagem(x,y+1)))/4;

It(x,y) <= (imagem(x,y) - imagemanterior(x,y) + imagem(x+1,y)- imagemanterior(x+1,y) +imagem(x,y+1)- imagemanterior(x,y+1) + imagem(x+1,y+1)- imagemanterior(x+1,y+1))/4;

end loop;

end if ;

end process;

end Behavioral;

Altera_Forum · ‎03-24-2016

and the main code called hornshunck is this:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_signed.ALL;

use IEEE.STD_LOGIC_TEXTIO.ALL;

use ieee.numeric_std.all;

package imagens is

type image_array is array(0 to 49, 0 to 49) of signed(8 downto 0);

type image_derivadas is array(0 to 49, 0 to 49) of signed (9 downto 0);

type image_19bits is array (0 to 49, 0 to 49) of signed (18 downto 0);

end imagens;

use work.imagens.all;

--type image_array is array(0 to 49, 0 to 49) of unsigned(7 downto 0);

entity hornschunk is

Port ( clk_0 : in bit;

ukfinal : out image_19bits ;

vkfinal: out image_19bits

);

end hornschunk;

architecture Behavioral of hornschunk is

signal entrada, entradaanterior : image_array;

signal Ix_0,Iy_0,It_0, dividendo_0 : image_derivadas;

signal divisor_0, uk_0, vk_0: image_19bits;

signal mediau_0, mediav_0, uk2_0, vk2_0,uk3_0,vk3_0, mediau2_0,mediav2_0,dividendo2_0,dividendo3_0: image_19bits;

--signal uk_0,vk_0,uk_1,vk_1,divisor_0 : SIGNED (32499 downto 0) ;

component inicializacao port(

clk: in bit;

imagem: out image_array;

imagemanterior: out image_array

); end component;

--*component inicializacao port(

-- clk: in bit;

-- imagem: out SIGNED (19999 DOWNTO 0);

-- imagemanterior: out SIGNED (19999 DOWNTO 0)

-- ); end component;

-- */

component stage_1 port(

clk: in bit ;

imagem : in image_array;

imagemanterior: in image_array;

Ix: out image_derivadas;

Iy : out image_derivadas;

It : out image_derivadas

); end component;

--component stage_1 port(

-- clk: in bit ;

-- imagem: in SIGNED (19999 DOWNTO 0);

-- imagemanterior: in SIGNED (19999 DOWNTO 0);

-- Ix: out SIGNED (3 DOWNTO 0);

-- Iy : out SIGNED (3 DOwNTO 0);

-- It : out SIGNED (3 DOWNTO 0)

-- ); end component;

component stage_2

port(

clk: in bit;

Ix: in image_derivadas;

Iy: in image_derivadas;

It: in image_derivadas;

divisor: out image_19bits;

dividendo: out image_derivadas

--uk:out SIGNED (9999 DOWnTO 0);

--vk:out SIGNED (9999 DOWNto 0)

); end component;

component first_iteration

port(

clk : in bit;

divisor: in image_19bits;

dividendo: in image_derivadas;

Ix: in image_derivadas;

Iy: in image_derivadas;

--uk: in SIGNED (9999 DOWNTO 0);

--vk: in SIGNED (9999 DOWNTO 0);

uk1: out image_19bits;

vk1: out image_19bits

); end component;

component medias_1

port(

clk: in bit;

uk1: in image_19bits;

vk1: in image_19bits;

mediau: out image_19bits;

mediav: out image_19bits

); end component;

component second_stage_2

port(

clk: in bit;

Ix: in image_derivadas;

Iy: in image_derivadas;

It: in image_derivadas;

mediau: in image_19bits;

mediav: in image_19bits;

dividendo2: out image_19bits

); end component;

component second_iteration

port(

clk: in bit;

divisor: in image_19bits;

dividendo2: in image_19bits;

mediau: in image_19bits;

mediav: in image_19bits;

Ix: in image_derivadas;

Iy: in image_derivadas;

uk2: out image_19bits;

vk2: out image_19bits

); end component;

component medias_2

port(

clk: in bit;

uk2: in image_19bits;

vk2: in image_19bits;

mediau2: out image_19bits;

mediav2: out image_19bits

); end component;

component third_stage_2

port(

clk: in bit;

Ix: in image_derivadas;

Iy: in image_derivadas;

It: in image_derivadas;

mediau2: in image_19bits;

mediav2: in image_19bits;

dividendo3: out image_19bits

); end component;

component third_iteration

port(

clk: in bit;

divisor: in image_19bits;

dividendo3: in image_19bits;

mediau2: in image_19bits;

mediav2: in image_19bits;

Ix: in image_derivadas;

Iy: in image_derivadas;

uk3: out image_19bits;

vk3: out image_19bits

); end component;

begin

U1: inicializacao PORT MAP (

clk=> clk_0,

imagem=> entrada,

imagemanterior => entradaanterior

);

U2: stage_1 PORT MAP (

clk => clk_0,

imagem =>entrada,

imagemanterior => entradaanterior,

Ix=> Ix_0,

Iy=>IY_0,

It=>IT_0

);

U3: stage_2 PORT MAP (

clk => clk_0,

Ix =>Ix_0,

Iy =>Iy_0,

It => It_0,

divisor => divisor_0,

dividendo => dividendo_0

);

U4: first_iteration PORT MAP (

clk => clk_0,

divisor => divisor_0,

dividendo => dividendo_0,

Ix => Ix_0,

Iy=> Iy_0,

uk1 => uk_0,

vk1 => vk_0

--uk1 => ukfinal,

--vk1 => vkfinal

);

U5: medias_1 PORT MAP(

clk => clk_0,

uk1 => uk_0,

vk1 => vk_0,

mediau => mediau_0,

mediav =>mediav_0

);

U6: second_stage_2 PORT MAP(

clk => clk_0,

Ix => Ix_0,

Iy => Iy_0,

It => It_0,

mediau => mediau_0,

mediav => mediav_0,

dividendo2 => dividendo2_0

);

U7: second_iteration PORT MAP(

clk => clk_0,

divisor => divisor_0,

dividendo2 => dividendo2_0,

mediau => mediau_0,

mediav => mediav_0,

Ix => Ix_0,

Iy => Iy_0,

uk2 => uk2_0,

vk2 => vk2_0

);

U8: medias_2 PORT MAP(

clk => clk_0,

uk2 => uk2_0,

vk2 => vk2_0,

mediau2 => mediau2_0,

mediav2 =>mediav2_0

);

U9: third_stage_2 PORT MAP(

clk => clk_0,

Ix => Ix_0,

Iy => Iy_0,

It => It_0,

mediau2 => mediau2_0,

mediav2 => mediav2_0,

dividendo3 => dividendo3_0

);

U10: third_iteration PORT MAP(

clk => clk_0,

divisor => divisor_0,

dividendo3 => dividendo3_0,

mediau2 => mediau2_0,

mediav2 => mediav2_0,

Ix => Ix_0,

Iy => Iy_0,

uk3 => uk3_0,

vk3 => vk3_0

);

end behavioral;

Altera_Forum · ‎03-24-2016

You've commented out the numeric std package.