`quartus_syn` was unexpectedly terminated by signal 6

[Wes]

I am trying to compile a design targeting an Agilex (AGFB027R31C3I3V) and during the Analysis & Synthesis phase it quits with the following error (no other context): 

Error(20549): Current module quartus_syn was unexpectedly terminated by signal 6. This may be because some system resource has been exhausted, or quartus_syn performed an illegal operation. You can view system resource requirements on the System and Software Requirements page of the Intel FPGA website (https://fpgasoftware.intel.com/requirements/). 

I have seen a similar error before when compiling on a server with insufficient RAM, but the machine being compiled on now has over 300GB of RAM.

Operating System: CentOS 7, Linux kernel 3.10.0

[SyafieqS]

Hi,

Can you try to recompile it? delete the .qdb folder and rerun the flow see if it resolve the issue.

[Wes]

Thanks for the reply!

Unfortunately this results in the same error.

[SyafieqS]

Hi,

Is it possible to attach the qar achieve design here for me to reproduce the issue?

[SyafieqS]

Wes,

May I know if there is any update from my previous reply?

[SyafieqS]

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 10/10 survey