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"Force Use of Synchronous Clear Signals" assignment

LMelo2
Beginner
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Good morning. I need to force the position of a particular register on DDIOOUTCELL. The "Location -> DDIOOUTCELL_X34_Y18_N4" assignment works correctly. Also I need to use the SCLR, SLOAD and SDATA pins of that particular register. With the "Force Use of Synchronous Clear Signals" assignment I am able to reset the register, but I cannot find any assignment to force the synchronous LOAD. Can you help me?

regards, Luca

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sstrell
Honored Contributor III
630 Views

sload is used to set a value from a separate sdata input.  You're just setting the output to 1 when this signal is enabled, which is not the intended behavior.  If the device doesn't support this configuration (which seems to be the case) extra logic is added to give you the behavior you've defined.

Maybe what you really want is an asynchronous preset, which would set the output to 1 whenever enabled.

You should check the Design Recommendations user guide to see how to code for what you want:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/user-guides.html

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sstrell
Honored Contributor III
639 Views

How are you coding this?  It would be based on that.

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LMelo2
Beginner
631 Views
here is an example:
I create in vhdl the model of the FF I need:

DFF:process(clk_10M_int)is
begin

if rising_edge(clk_10M_int)then
if(sclr='1')then
Qdata<='0';
elsif(sload='1')then
Qdata<='1';
else
Qdata<=Ddata;
end if;
end if;

end process DFF;

then I fix the register position on a register (one of 2) outgoing DDRs with the following line in 
the .qsf file:
set_location_assignment DDIOOUTCELL_X34_Y10_N11 -to Qdata~reg0
At this point Quartus creates the circuit of the 1st photo:
DFF.png


then I always add this line in the .qsf file: 
set_instance_assignment -name FORCE_SYNCH_CLEAR ON -to Qdata ~ reg0
 
Now Quartus creates this circuit:
DFF2.png


 
So I can activate the synchronous reset of that register, 
but I don't know how to activate the synchronous load
 
 
Basically, Quartus uses combinatorial logic to create the "sync_load" function, as seen in this photo:
3.png
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sstrell
Honored Contributor III
631 Views

sload is used to set a value from a separate sdata input.  You're just setting the output to 1 when this signal is enabled, which is not the intended behavior.  If the device doesn't support this configuration (which seems to be the case) extra logic is added to give you the behavior you've defined.

Maybe what you really want is an asynchronous preset, which would set the output to 1 whenever enabled.

You should check the Design Recommendations user guide to see how to code for what you want:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/user-guides.html

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LMelo2
Beginner
624 Views
thank you very much for your time
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RichardTanSY_Intel
606 Views

I’m glad that your question has been addressed. With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.


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