"HPS Boot First" vs "FPGA Boot First" Mode (Stratix 10 SoC Dev Kit)

[jwdonal]

Hello all,

I've been reading up on boot modes for stratix 10 in the ug-s10-soc-boot.pdf (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-s10-soc-boot.pdf) document. I have several questions regarding these two boot modes.

Question 1) What specifically is it that tells the SDM which boot mode it should follow? That is, how does it know which to perform?

Figure 5 and Figure 10 in ug-s10-soc-boot.pdf show what the contents of flash should look like for each of the modes. So one would assume that the SDM knows which boot mode to perform based on the contents of the flash. However, this appears not to be the case. Why do I say this? Because I generated the flash programming files for both modes (using instructions in sections 1.6.1 and 1.6.2 of the programmer user guide found here: https://www.intel.com/content/www/us/en/programmable/documentation/ftt1513991830769.html) and was greatly surprised by the fact that the JIC file that was generated for each mode were binary identical to each other. Ummm...what? How can that be? I generated the files using the GUI (as given in the instructions in the link) but also generated the files using the quartus_pfg command line tool. The result was the same in both cases.

I received a slightly different set of files depending on the boot first mode that I chose, but again the JIC files that were generated in both cases were a binary match. This makes no sense.

It's pretty clear from the ug-s10-soc-boot.pdf document that the 2 JIC flash files for the SDM flash should be:

1. Quite different from one another (e.g. flash contents for HPS boot first mode does not contain the FPGA Core or FPGA I/O config data)
2. Different sizes or at least one should have a lot more unused flash space than the other (e.g. the flash contents for the HPS boot first mode should have significantly less valid data contents in it since it contains no FPGA core or I/O config information)

Since it is the case that the two JIC files are binary identical in both modes I have to assume that the SDM determines HPS-first or FPGA-first boot mode from some other means. So what is it?

Question 2) What are these *_hps_auto.sof files that the tool generates?? Regardless of whether I use the GUI approach or the command line approach for generating these programming files I always get these weird extraneous *_hps_auto.sof files that I have no idea what to do with. I have been unable to find documentation on what these *_hps_auto.sof files are used for or what I should do with them. Where are these files documented and what do they do? Are they important? Can I delete? If I don't need them is there an option to stop them from being generated in the first place?

Thank you for your help.

[EBERLAZARE_I_Intel]

Hi,

I will try to answer both questions as much as possible, 

Q1) Though which boot should be first, I do no think there should be file size different, as the settings may just be 1 line of string settings changes. I may need to reconfirm this. There seems to be an issue accessing the document that you pointed out. 

Q2) I generate a S10 design file but never seen the file you mentioned, it may be your sof design file based on your Quartus project name. Can you recheck?

[EBERLAZARE_I_Intel]

Hi,

Do you have any update on this?

[JonVandenbruaene]

I think the hps_auto.sof file is a FPGA FIRST SOF file that can be loaded over JTAG.