When I use the rapid recompile (signal tap logic analyzer flow, quartus std 21.1.0 Build 842) : out of memory (even with 64 GB or RAM).
Cyclone V FPGA, used at around 50%.
When I use the normal compile it works and uses about 10 GB or RAM (win 10).
Is there a rapid recompile bug?
May be you can delete db and incremental_db file (Standard/Lite) or qdb file (Pro) then recompile again. If the error still persist, may be you can try with larger RAM memory because place and route stage usually consumes more RAM compared to others.
Ok I will try to delete db / incremental_db then see if rapide recompile works.
I noticed on the web that quartus has rapide compile issue with smart recompile enabled (set_global_assignment -name SMART_RECOMPILE ON) (which keeps data in incremental_db).
It has maybe not been fixed yet?
rapid recompile is not available when deleting the incremental_db/db directories, which makes sense.
Turning off smart compilation does not help.
Note that the normal compile flow uses about 10 GB.
Looks like there is an issue with rapid recompile in certain RTL code situation.
I had no issue with rapid recompile before I added a Synplify VQM,
which fills much more the FPGA, but still. Maybe that rapid recompile has issue when .vqm is used.
May be you can check in task manager real time memory usage during rapid recompile. Is there any spike up consumes and exceeds the whole 64GB RAM?
Probably larger RAM memory is required for rapid recompile of Synplify VQM. Since there is no extra RAM available with you for now you may stick with normal compilation first.
Let me know if the problem still exists even after expanding the RAM memory.
Let me know also if any further updates or concerns.
Since there are no further concerns for this thread, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you.