recommended Quartus Prime version for Stratix IV

[Hermann]

Hello,

I'm working on upgrading an older design made for a Stratix IV FPGA with new features. For this I want to use the latest available Quartus Prime software supporting it. In both the Prime Standard Edition 20.1.1 and 21.1 I succeeded to upgrade the IP to the latest version coming with the design tools. The design includes a PCIe and DDR3 controller. Both are showing errors when trying to generate them in platform designer. The PCIe controller seems to need a ip_compiler library that is missing and the DDR3 core fails to generate and compile a sequencer executable.

So, what is the best software to use to design and route the Stratix IV GX family today ?

Best regards

Hermann

[sstrell]

Can you show the exact errors?  You should be able to upgrade those cores in the latest versions.  If not, you can just recreate them with the same parameters and that usually fixes issues.

[Hermann]

The DDR3 core gives me these errors. I tried several different DDR3 presets. They all gave me this error:

Error: s0: Error during execution of "{C:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: s0: Execution of command "{C:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: s0: /mnt/c/intelfpga/21.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../hDVS_top_mem_if_ddr3_emif_0_s0_AC_ROM.hex -inst_rom ../hDVS_top_mem_if_ddr3_emif_0_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000110001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100110000 -DAC_ROM_MR1=0000000000000 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000001000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001001001001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001011001000 -DAC_ROM_MR1_MIRR=0000000000000 -DAC_ROM_MR2_MIRR=0000000010000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0
Error: s0: UniPHY Sequencer Microcode Compiler
Error: s0: Copyright (C) 2021 Intel Corporation. All rights reserved.
Error: s0: Info: Reading sequencer_mc/ac_rom.s ...
Error: s0: Info: Reading sequencer_mc/inst_rom.s ...
Error: s0: Info: Writing ../hDVS_top_mem_if_ddr3_emif_0_s0_AC_ROM.hex ...
Error: s0: Info: Writing ../hDVS_top_mem_if_ddr3_emif_0_s0_inst_ROM.hex ...
Error: s0: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: s0: Makefile:27: recipe for target 'mc' failed
Error: s0: child process exited abnormally
Error: s0: Cannot find sequencer/sequencer.elf
Error: s0: An error occurred
while executing
"error "An error occurred""
(procedure "_error" line
invoked from within
"_error "Cannot find $seq_file""
("if" then script line 2)
invoked from within
"if {[file exists $seq_file] == 0} {
_error "Cannot find $seq_file"
}"
(procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
invoked from within
"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""
invoked from within
"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"
("if" then script line 2)
invoked from within
"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."
(procedure "generate_qsys_sequencer_sw" line 943)
invoked from within
"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."
invoked from within
"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."
("if" else script line 2)
invoked from within
"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {
set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."
(procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"
invoked from within
"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"
(procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"
invoked from within
"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {
set file_name [file tail $genera..."
(procedure "generate_synth" line
invoked from within
"generate_synth hDVS_top_mem_if_ddr3_emif_0_s0"
Error: Generation stopped, 97 or more modules remaining
Error: qsys-generate failed with exit code 1: 15 Errors, 27 Warnings

The PCIe core creates these error messages:

Error: altgx_internal: error copying "C:/intelfpga/21.1/quartus/../ip/altera/ip_compiler_for_pci_express/lib/altpcie_serdes_4sgx_x8d_gen1_08p.v": no such file or directory
while executing
"file copy -force $source_file $outdir/$output_file"
(procedure "my_generation_callback" line 73)
invoked from within
"my_generation_callback"
Error: altgx_internal: Generation callback did not provide a top level file (expected `add_file $output_dir/hDVS_top_pcie_altgx_internal.v|vhd|sv {SIMULATION SYNTHESIS}`)
Error: Generation stopped, 47 or more modules remaining
Error: qsys-generate failed with exit code 1: 3 Errors, 22 Warnings

The second error I resolved by copying over the old IP_COMPILER libraries from an older version of Quartus.

regards

Hermann

[RichardTanSY_Intel]

Which OS are you using? If window, have you installed the WSL?

You need to install WSL followed by a Linux distribution for Nios Command Shell to work in Windows:

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2019/how-do-i-install-the-windows--subsystem-for-linux---wsl--on-wind.html

[RichardTanSY_Intel]

I think this is related to the KDB below, could you try to install the patch and see if it works.

https://www.intel.com/content/www/us/en/support/programmable/articles/000088789.html

[RichardTanSY_Intel]

May I know does my latest reply helps in your issue?

[Hermann]

Hello

I'm sorry for the late answer. I followed your advice and some others I found and succeeded to route the FPGA now. Main trick was to install the Linux version on an Ubuntu box. In addition I needed to follow this advice to get the tool chain set up:

https://www.intel.com/content/www/us/en/support/programmable/articles/000086438.html?

Thank you for your help

Best regards

Hermann

[RichardTanSY_Intel]

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.