Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17255 Discussions

report timing with Tcl in QuartusII 11.0

Altera_Forum
Honored Contributor II
1,641 Views

Hi: 

I'm trying to report timing with Tcl in QuartusII, first I open a project and constraint the clock about 125MHz, after compile the project, I want to see the actual fmax, I use Tcl to report the timing, my Tcl commands is as follow: 

load_report $project_name puts  

But when I use the command "get_timing_analysis_summary_results",come an error "Error:ERROR: Can't find panel: Timing Analyzer||Timing Analyzer Summary. Specify an existing report panel name" 

I konw in QuartusII 11.0, Classic Timing Analyzer is away, is this a reason? 

Thanks!
0 Kudos
4 Replies
Altera_Forum
Honored Contributor II
548 Views

Cant you see the Fmax in the compilation report?

0 Kudos
Altera_Forum
Honored Contributor II
548 Views

Yes, the whole compile flow is OK!

0 Kudos
Altera_Forum
Honored Contributor II
548 Views

The get_timing_analysis_summary_results can only be used with the Classic Timing Analyzer.

0 Kudos
Altera_Forum
Honored Contributor II
548 Views

OK, thank you for reply , the problem is resolved. 

The command in QuartusII 8.1 is OK
0 Kudos
Reply