Re: schematic, bus explode, please

Altera_Forum · ‎05-08-2011

Hello friends,

I need to feed LPM_ADD_SUB module which is on 37 bits with only 21 bits and the rest tied to gnd (MSB's). The problem is I can't figure out how, since those 21 bits are from LPM_MULT and the bus name is result[21..0] and the input of LPM_ADD_SUB wants datab[36..0].

I know this is simple but I haven't found yet and keep me nervous :)

Thanks,

Altera_Forum · ‎05-08-2011

ok, still isn't working, I wrote a small verilog to concatenate buses like that

module conv21to37(in,out);
input in;
output out;
assign out = {16'b0000000000000000,in};
endmodule

But Quartus keep telling me

Error: Port "datab[0]" does not exist in macrofunction "inst13"

Error: Port "datab[10]" does not exist in macrofunction "inst13"

Error: Port "datab[11]" does not exist in macrofunction "inst13"

Error: Port "datab[12]" does not exist in macrofunction "inst13"

Error: Port "datab[1]" does not exist in macrofunction "inst13"

Error: Port "datab[2]" does not exist in macrofunction "inst13"

Error: Port "datab[3]" does not exist in macrofunction "inst13"

Error: Port "datab[4]" does not exist in macrofunction "inst13"

Error: Port "datab[5]" does not exist in macrofunction "inst13"

Error: Port "datab[6]" does not exist in macrofunction "inst13"

Error: Port "datab[7]" does not exist in macrofunction "inst13"

Error: Port "datab[8]" does not exist in macrofunction "inst13"

Error: Port "datab[9]" does not exist in macrofunction "inst13"

The macrofunction "inst13" is a LPM_MULT which is output 21 bits that I want to send into LPM_ADD_SUB which has a 37 bit bus on datab[36..0]

Any idea?

Altera_Forum · ‎05-09-2011

--- Quote Start ---

ok, still isn't working, I wrote a small verilog to concatenate buses like that

module conv21to37(in,out);
input in;
output out;
assign out = {16'b0000000000000000,in};
endmodule