signal II tap issue with I/O BUS

[Altera_Forum]

Hello and thanks for any help. 

 I am using signal II tap to debug an I/O Bus between FPGA and DSP. My design works fine in timing simulation and I do see my "BUS~result" showing count up to the DSP synchronized to a common clock between the two devices.  However in signal II tap my bus is always showing <0000>, the weird thing is that if I tap into the count signal that feeds the BUS signal I do see the count up working but not on the actual BUS signal.   Any remarks are greatly appreciated.  thx, Mowa...

[Altera_Forum]

Are you sure the count signal is feeding the output pins? are these pins bidirectiona? if so are you actually driving them?

[Altera_Forum]

Thanks for the reply, 

 I am pretty sure I am driving them and the timing simulation confirms, the bus is bidirectional. I wonder if there is something funny about the PINS in S2T?

[Altera_Forum]

May be you better start with a fresh signaltap. 

I asked about bidirectional pins because a pitfall may occur if you are not driving it correctly at the right time. It could be the DSP chip is driving it with zeros.

[Altera_Forum]

thanks, 

 I will give it a shot. Are you aware of any special case where S2T can't access a Bidirectional Bus because some XYZ reason?