signed integer to std_logic_vector and vise versa

[Altera_Forum]

Hello Altera people ! 

I have two questions :  1 // I need to read a signed integer and compare it in vhdl ! Knowing that the output is std_logic (either vector or simple). how to do it ? what are the instructions !?  2// The component will be used as user peripheral in Qsys so I guess the input isn't considered as integer no ? the input is 32 bits how I can do my comparison as if it is signed integer ?!   thnx

[Altera_Forum]

use ieee.numeric_std.all; 

 signal slv : std_logic_vector(10 downto 0); signal uns : signed(10 downto 0);  uns <= SIGNED(slv);

[Altera_Forum]

--- Quote Start ---  use ieee.numeric_std.all;  signal slv : std_logic_vector(10 downto 0); signal uns : signed(10 downto 0);  uns <= SIGNED(slv);  --- Quote End ---    This is my favorite graphic on VHDL conversions: http://www.bitweenie.com/listings/vhdl-type-conversion/