simulate parameterized ip block dcfifo_mixed_widths

[AndyRea]

using this as a verilog module included in a design inside a vhdl wrapper, how do i get modelsim to pick up the dcfifo_mixed_widths ip block properly so it can run testbenches?

// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module parametrized_fifo#
(
parameter DATA_WIDTH=64,
parameter NUM_OF_WORDS=256,
parameter ALM_FULL_VAL=6,
parameter USEDW_ADDR_WIDTH=8 // log2 of NUM_OF_WORDS
)

(
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw,
almost_full);

input aclr;
input [DATA_WIDTH-1:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [DATA_WIDTH-1:0] q;
output rdempty;
output [USEDW_ADDR_WIDTH-1:0] rdusedw;
output wrfull;
output [USEDW_ADDR_WIDTH-1:0] wrusedw;
output almost_full;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

wire [DATA_WIDTH-1:0] sub_wire0;
wire sub_wire1;
wire [USEDW_ADDR_WIDTH-1:0] sub_wire2;
wire sub_wire3;
wire [USEDW_ADDR_WIDTH-1:0] sub_wire4;
wire [DATA_WIDTH-1:0] q = sub_wire0[DATA_WIDTH-1:0];
wire rdempty = sub_wire1;
wire [USEDW_ADDR_WIDTH-1:0] rdusedw = sub_wire2[USEDW_ADDR_WIDTH-1:0];
wire wrfull = sub_wire3;
wire [USEDW_ADDR_WIDTH-1:0] wrusedw = sub_wire4[USEDW_ADDR_WIDTH-1:0];
wire sub_wire5 = wrusedw[USEDW_ADDR_WIDTH-1];

assign almost_full = sub_wire5;

dcfifo_mixed_widths dcfifo_mixed_widths_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdusedw (sub_wire2),
.wrfull (sub_wire3),
.wrusedw (sub_wire4),
.eccstatus (),
.rdfull (),
.wrempty ());

defparam
dcfifo_mixed_widths_component.add_usedw_msb_bit = "ON",
dcfifo_mixed_widths_component.enable_ecc = "FALSE",
dcfifo_mixed_widths_component.intended_device_family = "Arria 10",
dcfifo_mixed_widths_component.lpm_hint = "DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT=TRUE",
dcfifo_mixed_widths_component.lpm_numwords = NUM_OF_WORDS,
dcfifo_mixed_widths_component.lpm_showahead = "OFF",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = DATA_WIDTH,
dcfifo_mixed_widths_component.lpm_widthu = USEDW_ADDR_WIDTH,
dcfifo_mixed_widths_component.lpm_widthu_r = USEDW_ADDR_WIDTH,
dcfifo_mixed_widths_component.lpm_width_r = DATA_WIDTH,
dcfifo_mixed_widths_component.overflow_checking = "ON",
dcfifo_mixed_widths_component.rdsync_delaypipe = 5,
dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
dcfifo_mixed_widths_component.underflow_checking = "ON",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
dcfifo_mixed_widths_component.wrsync_delaypipe = 5;

endmodule

[ShengN_Intel]

Hi,

What I can understand is you include the verilog module into VHDL wrapper. As for that, are you using VHDL for modelsim simulation?

Best regards,
Sheng

[ShengN_Intel]

Hi,

Any update?

Best regards,
Sheng

[ShengN_Intel]

Hi,

Since there are no feedback for this thread, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you.

Thanks,

Best regards,
Sheng