switch or elsif problems

[Altera_Forum]

Hi everybody, 

 I am currently using Quartus II 9.0sp2 Web Edition, i'm trying to make a program to add some bits depending of this "switch" https://www.alteraforum.com/forum/attachment.php?attachmentid=7151 .   i have 2 seven segments and 10 of this switches,   i need to program it in quartus so if the switch is in "up" position one seven segment shows 1, if two of them are "up" shows 2 etc, if all of them are in "middle" position both will show 0, if it's in "down" position the other one will show 1, 2 etc...  i have my code here but i receive this warning Warning: LATCH primitive "c[8]" is permanently disabled and my program just doesn't seem to work  library ieee;use ieee.std_logic_1164.all; entity ContadorDeVotos is port ( Switch: in std_logic_vector(9 downto 0); On1, On2 : buffer std_logic_vector(9 downto 0); outSup : buffer std_logic_vector(10 downto 0); outInf : buffer std_logic_vector(10 downto 0); Rta1, Rta2, Rta3, Rta4: buffer std_logic_vector(3 downto 0); outSuma1, outSuma2: buffer std_logic_vector(3 downto 0); outDeco1, outDeco2: out std_logic_vector(6 downto 0) ); end ContadorDeVotos; architecture RTL of ContadorDeVotos is signal c,d: std_logic_vector (9 downto 0); component SumadorCompleto port(a, b, c: in std_logic; s, Co: out std_logic); end component; component SumadorParalelo port( A, B: in std_logic_vector(3 downto 0); Cin: in std_logic; S: out std_logic_vector(3 downto 0); Cout: out std_logic); end component; component Decodificador port( bcd: in std_logic_vector(3 downto 0); led: out std_logic_vector(6 downto 0) ); end Component; begin process(Switch) begin IF(Switch(0)='1') THEN c(0)<='0'; d(0)<='1'; ELSIF(Switch(0)='0') THEN c(0)<='1'; d(0)<='0'; ELSIF(Switch(0)='-') THEN c(0)<='0'; d(0)<='0'; ELSIF(Switch(1)='1') THEN c(1)<='0'; d(1)<='1'; ELSIF(Switch(1)='0') THEN c(1)<='1'; d(1)<='0'; ELSIF(Switch(1)='-') THEN c(1)<='0'; d(1)<='0'; ELSIF(Switch(2)='1') THEN c(2)<='0'; d(2)<='1'; ELSIF(Switch(2)='0') THEN c(2)<='1'; d(2)<='0'; ELSIF(Switch(2)='-') THEN c(2)<='0'; d(2)<='0'; ELSIF(Switch(3)='1') THEN c(3)<='0'; d(3)<='1'; ELSIF(Switch(3)='0') THEN c(3)<='1'; d(3)<='0'; ELSIF(Switch(3)='-') THEN c(3)<='0'; d(3)<='0'; ELSIF(Switch(4)='1') THEN c(4)<='0'; d(4)<='1'; ELSIF(Switch(4)='0') THEN c(4)<='1'; d(4)<='0'; ELSIF(Switch(4)='-') THEN c(4)<='0'; d(4)<='0'; ELSIF(Switch(5)='1') THEN c(5)<='0'; d(5)<='1'; ELSIF(Switch(5)='0') THEN c(5)<='1'; d(5)<='0'; ELSIF(Switch(5)='-') THEN c(5)<='0'; d(5)<='0'; ELSIF(Switch(6)='1') THEN c(6)<='0'; d(6)<='1'; ELSIF(Switch(6)='0') THEN c(6)<='1'; d(6)<='0'; ELSIF(Switch(6)='-') THEN c(6)<='0'; d(6)<='0'; ELSIF(Switch(7)='1') THEN c(7)<='0'; d(7)<='1'; ELSIF(Switch(7)='0') THEN c(7)<='1'; d(7)<='0'; ELSIF(Switch(7)='-') THEN c(7)<='0'; d(7)<='0'; ELSIF(Switch(8)='1') THEN c(8)<='0'; d(8)<='1'; ELSIF(Switch(8)='0') THEN c(8)<='1'; d(8)<='0'; ELSIF(Switch(8)='-') THEN c(8)<='0'; d(8)<='0'; ELSIF(Switch(9)='1') THEN c(9)<='0'; d(9)<='1'; ELSIF(Switch(9)='0') THEN c(9)<='1'; d(9)<='0'; ELSIF(Switch(9)='-') THEN c(9)<='0'; d(9)<='0'; END IF; on1 <=c; on2 <=d; end process; SCS1: SumadorCompleto port map (On1(0), On1(1), On1(2), outSup(0), outSup(1)); SCS2: SumadorCompleto port map (On1(3), On1(4), On1(5), outSup(2), outSup(3)); SCS3: SumadorCompleto port map (On1(6), On1(7), On1(8), outSup(4), outSup(5)); SCS4: SumadorCompleto port map (On1(9), '0', '0', outSup(6),outSup(7)); SPS1: SumadorParalelo port map ("00" & outSup(1) & outSup(0) ,"00" & outSup(3) & outSup(2),'0', Rta1, outSup(8)); SPS2: SumadorParalelo port map ("00" & outSup(5) & outSup(4),"0000",outSup(6), Rta2, outSup(9)); SPS3: SumadorParalelo port map (rta1, rta2,'0', outSuma1, outSup(10)); DecoSuperior: Decodificador port map (outSuma1, outDeco1); SCI1: SumadorCompleto port map (On2(0), On2(1), On2(2), outInf(0), outInf(1)); SCI2: SumadorCompleto port map (On2(3), On2(4), On2(5), outInf(2), outInf(3)); SCI3: SumadorCompleto port map (On2(6), On2(7), On2(8), outInf(4), outInf(5)); SCI4: SumadorCompleto port map (On2(9), '0', '0', outInf(6),outInf(7)); SPI1: SumadorParalelo port map ("00" & outInf(1) & outInf(0) ,"00" & outInf(3) & outInf(2),'0', Rta3, outInf(8)); SPI2: SumadorParalelo port map ("00" & outInf(5) & outInf(4),"0000",outInf(6), Rta4, outInf(9)); SPI3: SumadorParalelo port map (rta3, rta4,'0', outSuma2, outInf(10)); DecoInferior: Decodificador port map (outSuma2, outDeco2);  i just started using quartus a couple of days ago and i'm pretty new of this, sorry if my mistake is obvious.  sorry for my bad english but english isn't my mother language, still i can read it pretty well, if you can help me i'll be grateful.  thank you.

[Altera_Forum]

regarding your switch statement. in this case you don't need if. 

just say: c <= not switch; d <= switch;  your '-' is not needed. But haven't checked the rest of your code.

[Altera_Forum]

Two points to consider: 

- don't care '-' isn't a std_logic value you can check for. Only '0' and '1' are valid input values. - you apparently didn't think well about the intended operation of your logic. By nature of the "if then elsif else" chain, only one of all lines can be active at a time. So most bits wil be never assigned a value.

[Altera_Forum]

nevermind what i said before, thank you kaz you response solved my problem,now i just have one question, like i said in my first post i need my "switch" to function as the switch i showed you in my image, i don't know it's name in english sorry, i want my "switch" to have some kind of option "off" so when i am simulating in the waveform file both of the vectors c and d are in "0" 

thank you again.