synthese

[Altera_Forum]

hello 

I have a code in vhdl ,I want to do the synthese under quartus   can you give me the steps to the synthesis in quartus

[Altera_Forum]

open quartus => file => new project wizard => decide a unique folder for your project files, give it name same as top level of your vhdl. 

 then go to project(menu) => add files and add your top level and all related sumodules.  decide a device from assignments menu => device  create and add an sdc file for timing.  click on compile button (or => processin => start compilation) and enjoy...

[Altera_Forum]

how to do this step 

create and add an sdc file for timing.

[Altera_Forum]

You can jump that step, but your FPGA might not work properly if you do. 

 To create and add an sdc file for timing you will need to read the Timequest chapter 6 and 7 of the QuartusII user manual. http://www.altera.com/literature/hb/qts/qts_qii5v3_02.pdf

[Altera_Forum]

For a starter use this example from timequest design centre: 

 http://www.altera.com/support/examples/timequest/exm-tq-basic-sdc-template.html