system verilog signed'() extended sign bit wrong

[RRoma13]

module signed_test3(
input logic clk,
input logic [11:0] in,
input logic [11:0] zero,

output logic signed [15:0] d,
output logic signed [15:0] d2
);
logic signed [15:0] c,c2;
logic signed [11:0] a,b;
always_ff @(posedge clk) begin
a <= in;
b <= signed'( a[11:0] );
c <= ( signed'( b + signed'(zero) ) );
c2 <= ( signed'( b[11:0] + signed'(zero) ) );
end
assign d = signed'( c );
assign d2 = signed'( c2 );
endmodule

if you wrote only name of signed signal synth reduce sum to one bit.

of course all simulators(edaplayground) and Mentor Precision work as described - 

12bit of signed "b" + 12 bit signed "zero"  = signed value extended to 16 bit "c".

quartus 21.1

[Paveetirra_Srie]

Hi RRoma13,

I'm unclear about your query. Could you kindly explain further?

Thanks

Regards,

Pavee

[RRoma13]

the apotheosis of this situation

module signed_test3(
input logic [11:0] a,
input logic [11:0] a1,
output logic [11:0]b,
output logic [11:0]b1
);

assign b[11:0] = unsigned'({a[11],a[10:0]});
assign b1[11:0] = unsigned'(a1[11:0]);

endmodule

see screenshot of rtl viewer

[RRoma13]

if this module set as top level in quartus and run synthesis, then  summator for signal c and c2 is different. for c2 is right. but for signal "c" is wrong. quartus reduce result of sum to one bit and connect this bit to all bits of register "c".(see picture of rtl viewer). like c[15:0]={{sum[0]}}.

and all simulators and Mentor Precision work normally, c and c2 is same.

[Paveetirra_Srie]

Just wanted to check with you, is your concern has been addressed?

If yes , kindly do let me know.

Thank You

[Paveetirra_Srie]

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