Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16704 Discussions

timing path has same from and to nodes.

CosmoKramer
Employee
539 Views

This is in the timing report and it is frustrating.  Why are from and to nodes same? How to read this timing path? 

 

From Node ; module|testfifo|empty~_Duplicate ;
To Node ; module|testfifo|empty~_Duplicate ;
Launch Clock ; somethingA|somethinB|ch0 ;
Latch Clock ; somethingA|somethinB|ch0 ;
; Data Arrival Time ; 9.774 ;
; Data Required Time ; 9.596 ;
; Slack ; -0.178 (VIOLATED)

0 Kudos
3 Replies
sstrell
Honored Contributor III
512 Views

Can you provide more detail on the design, target device, SDC constraints, etc.?  It's hard to tell what's happening here.  The path could be a feedback loop.

0 Kudos
Nurina
Employee
503 Views

Hello,


Can you share the .qar file of your project?

To do this, go to Project>Archive Project


Regards,

Nurina



0 Kudos
Nurina
Employee
441 Views

Hello,


Can you provide some updates?


Regards,

Nurina


0 Kudos
Reply