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used logic elements increase rapidly!

Altera_Forum
Honored Contributor II
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Hi, all. 

I am creating sopc builder system with nios II-f processor and some other components. After compiled, 48% the total logic elements are used. 

 

but, when i added a dma component to the system, the used logic elements increased rapidly from 48% to more than 100%. 

 

Can anybody help me out from puzzled? 

 

Regards.
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Altera_Forum
Honored Contributor II
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Did you notice a bunch of adapters generated? They should have names like "clock_0.v" or "burst_0.v"..... or something similar. If you connect the DMA masters to everything in your system I would expect the fabric to grow substantially as well.

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Altera_Forum
Honored Contributor II
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Thanks for your attention and forgive for my late reply. 

 

There are files like "burst_0.v" in my folder as I enable the burst option for my nios II, but it's not the main factor because they had been there before I added the DMA. 

 

I had found out the cause while I compare the "Resource Utilization by Entity" reports. I had used a dc-fifo in my sopc system, which changed to use register resources after the dma component had been added. However, it is supposed to use memory resources

 

I still don't konw how to make the fifo use memory resources forever.
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Altera_Forum
Honored Contributor II
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It sounds like you ran out out of on-chip memory resources and now some FIFOs are being implemented in LEs/ALUTs. I would inspect you on-chip memory utilization to see if you are running low. The DMA has an option where you can force it's internal FIFO into logic instead of RAM. That FIFO is pretty shallow so if you are tight on memory that would be a good one to force into LEs/ALUTs.

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Altera_Forum
Honored Contributor II
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I used cyclone III, which has about 64Kbytes of ram memory, and I have used less than 50%.  

 

And the fifo which runs out my LEs is a dc-fifo which is used on my video pipeline. It uses 8K LEs instead of ram memory after I add a DMA. 

 

The DMA's internal fifo is small, so it doesn't matter whether to use LEs or Ram resources. 

 

I guess the fifo auto changes to use LEs while the system goes complex, so that it can get a better timing.
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Altera_Forum
Honored Contributor II
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Are you sure those memories are not under utilized though? For example if you create a memory that contains only four bytes, you will end up consuming an entire M9K block. You can see the block usage in the final compilation report.

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Altera_Forum
Honored Contributor II
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Yes, I compared the "Resource Utilization by Entity" reports. The fifo formally uses 8K memorys, then changes to use 8K registers. 

 

And now I reduce the size of the fifo to avoid LE resources to run out.
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