working with Quartus 8+Synplify DSP + Synplify PRO

[Altera_Forum]

Hi all, 

 I'm working on a undergraduate final project, and I use SynplifyDSP to implement a video improvement algorithm. The problem I faced - In my algorithm I have to access external memory in between two parts of the algorithm, so to do so I divided my Synplify DSP project into several blocks (in several files), I then synthesized each one separately (firstly I created VHDL in Synplify DSP and then went to Synplify PRO and ran a synthesis there). This have created several VQM's that I then inserted into Quartus.  When I then compile the project, I get errors -  things like undeclared pins etc. I think that this happens because Synplify DSP creates blocks with same names when working on different files.  I tried to combine the entire project into one file, but then when I choose retiming in synplify I didn't get the frequency I need (but when I synthesize each part on its own, I do get it to work fast enough).  My only conclusion - I must find a way to force the SynplifyDSP\PRO to generate different names, so I would be able to combine it all in Quartus, and thus hold the minimum frequency I need.  any ideas on how I can to that?  I would really appreciate any help...  thanks, Bulzeye  P.S. sorry for my English...

[Altera_Forum]

--- Quote Start ---  Yes,you are right.   I simulated each part separately - and they worked in simulation. I'm now simulating the entire project (it takes some time)  I also tested the non Synplify related stuff - and they work too .  I have a question - when I update my qxp files - what do I have to do to update them in the main project? What I do now is the following: I delete the "imported partitions" folder in the project library, I then overwrite the old qxp files. In quartus I select all the partitions - right click - import, and I press ok (when "reimport using latest files from previous location" is selected). Is this correct?  --- Quote End ---    Hi,  unfortunately I don't have the old Quartus Version available.   "Overwrite the old qxp file" means you are running the speparate Quartus project again and after that you export the design as design partition again ?  If yes, it should be ok.  Kind regards  GPK

[Altera_Forum]

Yes - that is what I meant. 

 Any other things I should check?

[Altera_Forum]

--- Quote Start ---  Yes - that is what I meant.  Any other things I should check?  --- Quote End ---    Hi,  what misbehaviour shows your design running of the FPGA ?  Look into your reports of the main Quartus project. Look for strange messages ( e.g Latches, Pins stuck ground .... ) and timing violations.  Which simulation do you use ?  Kind regards  GPK

[Altera_Forum]

have you taken a look at warning messages in both tools? done a gate level simulation? are your resets done properly?

[Altera_Forum]

As I'm using GiDEL card - I have many warnings that are related to their parts of the project (including timing error). But I don't use these parts, they are declared but that's it. 

 What I see is that all my data outputs from the blocks are stuck at GND,  even though input to it are correct (I used SignalTap to see these results)  I want to remind you that my project was already working - except it didn't hold timing - when I combined the entire project in SynplifyDSP and not in Quartus (meaning - I combined before I synthesized) so I'm somewhat beliving that the problem is somewhere with my usage of the tools - not a design problem... :confused: But again.. I could be wrong.  Ps - not so much related - is there a way to automatically insert registers? Or must I register manually every connection?  thanks again!

[Altera_Forum]

--- Quote Start ---  As I'm using GiDEL card - I have many warnings that are related to their parts of the project (including timing error). But I don't use these parts, they are declared but that's it.  What I see is that all my data outputs from the blocks are stuck at GND,  even though input to it are correct (I used SignalTap to see these results)  I want to remind you that my project was already working - except it didn't hold timing - when I combined the entire project in SynplifyDSP and not in Quartus (meaning - I combined before I synthesized) so I'm somewhat beliving that the problem is somewhere with my usage of the tools - not a design problem... :confused: But again.. I could be wrong.  Ps - not so much related - is there a way to automatically insert registers? Or must I register manually every connection?  thanks again!  --- Quote End ---    Hi,  maybe it is now a good time where we should summarize what we know. Please post your comments to my points.  1. You have a project where all is running. In this project you did not split your design, but you don't get the required clock speed. Is it not possible in SynplifyDSP to add some pipeline delay in order to speedup the design ?  2. In order to achieve timing closure you split your design and introduced an "external" memory. Is that memory outside of the FPGA or means "external" it is outside your original design ? How did you split the design ?  You run two SynplifyDSP ( generates the VHDL ) and SynplifyPro (generates the vqm files) projects. After that you run two speparate Quartus project in order to synthesis the two blocks ( necessary due to the module name problems of SynplifyDSP). After that you import the two blocks into your main project as <>.qxp file. You run a simulation for each block using the vqm file generated by SynplifyPro. After solving some problems ( implementation as LE, switch from VHDL to verilog) the simulation shows the expected results.  3. For your main project you need a toplevel. How is it generated ? Did you run a simulation of the main project with the imported blocks included ? Which simulator do use for simulation Quartus or modelsim ?  4. You run sucsesfully a P&R with Quartus, but after downloding to FPGA the design did not work.  Have a look to the resource utilization of your imported blocks. Something strange ( only a few LE or so ...) ? Did you get still warnings regarding .... stuck at ground or VCC . What about timing violations ? Did you achieve the required clock frequency ?  Can you please post your toplevel ?  Have a nice weekend  GPK

[Altera_Forum]

--- Quote Start ---  Hi,  maybe it is now a good time where we should summarize what we know. Please post your comments to my points.  1. You have a project where all is running. In this project you did not split your design, but you don't get the required clock speed. Is it not possible in SynplifyDSP to add some pipeline delay in order to speedup the design ?  it is possible to pipeline - and i actually do use this. however - when i do this to every part on its own - i get the needed frequency (or higher), but when i pipeline the entire project - it fails to reach those frequencies. in the log i can see how much register levels it has inserted - when i do this separately i end up with approx 80 register levels, but when i do this on the entire project - all i get is less than 10. because of that i thought that synplify must have problems with large designs - and went on to splitting it.    2. In order to achieve timing closure you split your design and introduced an "external" memory. Is that memory outside of the FPGA or means "external" it is outside your original design ? How did you split the design ?  i'm now using internal memory (fpga mram and m4k) - but eventually i would have to use onboard ddrii memory. i use the memory to implement parts of the algorithm (like transpose operation and flips etc... )  the design was actually split all the time - two parts of synplifydsp, memory part, another synplifydsp part and finally another memory part. what i did in the beginning is importing the entities of the memory blocks into synplifydsp (as black boxes) and synthesizing the entire project in synplify, getting a large vqm (that includes the memory + synplify) that i inserted into quartus and then i have done a p&r- this ended up with low frequency. i then started from the beginning: went to quartus - and built there the entire project again - this time importing the smaller synplify parts into quartus (at first - as vqm, later - as design partitions) i compile, and after successful p&r i load to the fpga - and it doesn't work.  You run two SynplifyDSP ( generates the VHDL ) and SynplifyPro (generates the vqm files) projects. After that you run two speparate Quartus project in order to synthesis the two blocks ( necessary due to the module name problems of SynplifyDSP). After that you import the two blocks into your main project as <>.qxp file. You run a simulation for each block using the vqm file generated by SynplifyPro. After solving some problems ( implementation as LE, switch from VHDL to verilog) the simulation shows the expected results.  yes.  3. For your main project you need a toplevel. How is it generated ? Did you run a simulation of the main project with the imported blocks included ? Which simulator do use for simulation Quartus or modelsim ?  i use the built in simulator in quartus. i have a top level file which i get from the card manufacturer, which calls a file that for me -the highest file in the hierarchy that i can still change.  this "high hierarchy file" is actually a .bdf file, that connects the entire parts, from input to output. every part - because i had to find a way to incintiate it - i created (manually) a .bdf file which holds only inputs and outputs, same as are in the qxp creating projects. simulation of the main project - don't work. i get exactly as i what i'm seeing in signaltap - a lot of pins are stuck at vcc/gnd. i spent hours going through different warnings i had - but could not find anything relevant.  4. You run sucsesfully a P&R with Quartus, but after downloding to FPGA the design did not run.  Have a look to the resource utilization of your imported blocks. Something strange ( only a few LE or so ...) ? Did you get still warnings regarding .... stuck at ground or VCC . What about timing violations ? Did you achieve the required clock frequency ?  the resource utilization looks ok. i do have several stuck at gnd/vcc, but they are from generated stuff (i think from synplifypro) and i don't know why is this, and what caused them. i also have several latch insertion - because of unsafe behavior - but it happens in a block i created and simulated lots of times. and also - the same block worked in the past. i realize that this might cause problems - and i'm now working on changing that vhdl file so that it won't have this problem.  i also get a timing error - but it has been there from day one, and it is from a part of the gidel generated top file - part of which i don't use.  Can you please post your toplevel ?   it is a problem to attach - it holds a big hierarchy.  Have a nice weekend  GPK  --- Quote End ---    thanks again!

[Altera_Forum]

--- Quote Start ---  thanks again!  --- Quote End ---    Hi,  I understand that you did not achieve the required clock frequency when you synthezise the design as a whole. How far are you away from the target ? If the difference is around 15-20% of the target you can still try to run the on the FPGA. The reason is that the default timing analysis is worst-case. That means low core voltage, highest temperature and slowest production process. If the design is running we can be sure that the design itself is ok. If the gap is too large or the design isn't running run a simulation of the design. As default the Quartus simulator uses a netlist with timing. Therefore you should reduce the clock frequence in the simulation. You can do that, because for the simulation results it is not important how fast the clock is. Alternativ you can run a functional simulation. For such simulation you have to generate an appropriate netlist. This could be done in the Quartus simulator. If this works we can also be sure that the design is ok.  Coming back to your hierachy. I understand following:  manufaturer_toplevel  -> "high hierachyfile.bdf" (Your toplevel)   -> DSP1,DSP2,MEM1,DSP3,MEM2  First you put high hierachyfile.bdf with all submodule in one project. Then you changed to separate vqm (Partitions) for DSP1,DSP2,MEM1,DSP3,MEM2 in order to achieve the  timing.   Now some questions about the retiming with SynplifyPro. When you synthesized the module separately, did you set a constraint for the inputs and outputs ? If not , SynplifyPro moves the registers without looking to input and output delays. As result it is possible that you get too long paths at the inputs and outputs after importing the design. To overcome this I would set tough requirements for input and output delays. Play a little  bit with the clock frequency setting, but avoid over-constraining.  Did you try for the whole design SynplifyDSP verilog output. Maybe retiming works better with verilog.  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,  I understand that you did not achieve the required clock frequency when you synthezise the design as a whole. How far are you away from the target ? If the difference is around 15-20% of the target you can still try to run the on the FPGA. The reason is that the default timing analysis is worst-case. That means low core voltage, highest temperature and slowest production process. If the design is running we can be sure that the design itself is ok. If the gap is too large or the design isn't running run a simulation of the design. As default the Quartus simulator uses a netlist with timing. Therefore you should reduce the clock frequence in the simulation. You can do that, because for the simulation results it is not important how fast the clock is. Alternativ you can run a functional simulation. For such simulation you have to generate an appropriate netlist. This could be done in the Quartus simulator. If this works we can also be sure that the design is ok.  the difference was quite large (approx. 50%), i did put it on the fpga but i got weird results on the screen - i thought they were because of the timing...  Coming back to your hierachy. I understand following:  manufaturer_toplevel  -> "high hierachyfile.bdf" (Your toplevel)   -> DSP1,DSP2,MEM1,DSP3,MEM2  correct.  the high hierarchy file contains more then just what listed on the bottom - but that's not relevant (i think).  First you put high hierachyfile.bdf with all submodule in one project. Then you changed to separate vqm (Partitions) for DSP1,DSP2,MEM1,DSP3,MEM2 in order to achieve the  timing.   yes.   Now some questions about the retiming with SynplifyPro. When you synthesized the module separately, did you set a constraint for the inputs and outputs ? If not , SynplifyPro moves the registers without looking to input and output delays. As result it is possible that you get too long paths at the inputs and outputs after importing the design. To overcome this I would set tough requirements for input and output delays. Play a little  bit with the clock frequency setting, but avoid over-constraining.  could you elaborate on that? all i did is setup a minimum frequency (which was about twice the frequency i need when i synthesized each part separately , and in the log i could see that it does achieve this frequency. how do i constrain the input\output correctly?  when i synthesized the entire project i set the min. freq. to be the actual min. freq. (because when i set it for higher - it didn't come even close to that) - and i didn't get my actual min. freq. just to be clear - i'm talking about 25.18mhz as my absolute minimum frequency.   Did you try for the whole design SynplifyDSP verilog output. Maybe retiming works better with verilog.  i did use verilog - i got the same results...  Kind regards  GPK  --- Quote End ---     thanks! Your help really saves me...

[Altera_Forum]

--- Quote Start ---  thanks! Your help really saves me...  --- Quote End ---    Hi,  50% off the required clock frequency will not work on the FPGA. You mentioned that you a have simulation of your complete design based on the speparate vqm files. Could you re-run this simulation with your single vqm file ? This is an important step, because if it rums we know that the source code is ok. Follow my recommendations in the previous post.  When you synthesize the blocks separately the tool needs to know the timing at the inputs and outputs. You have to keep in mind that you get paths between your blocks when you import them to your main project. Lets assume the driving block has an output and the receiving block an input register. When you now use retiming without constraints for the ports this register will be moved into your logic in order to achieve timing closure. But now you have longer paths at the in- and outputs. Without a constraint the tool assumes e.g that the data arrives without any delay ( 0.0ns) to the active clock edge. In your real design that will be not true.   In SynplifyPro setting an input delay describes the delay outside of your block before the signal arrives the input pin. Output signals drives logic outside your of block. The tool needs a information about the delay.  You can set both in the scope table in the tab "Inputs/Outputs" or directly in the sdc -file:  define_input_delay {porta[7:0] 4.0 -ref clk:r  Kind regards  GPK

[Altera_Forum]

using the single vqm implementation - the simulation works. 

 as regard to the input/output constraint - is it possible to constrain all the input/output at once? and also - how can I estimate this delay? and what if I push registers in Quartus between the blocks (in and out) - will they "stay put" there? (and then I will avoid constraining the inputs and outputs) - I think it would be ok. what do you think?

[Altera_Forum]

--- Quote Start ---  using the single vqm implementation - the simulation works.  as regard to the input/output constraint - is it possible to constrain all the input/output at once? and also - how can I estimate this delay? and what if I push registers in Quartus between the blocks (in and out) - will they "stay put" there? (and then I will avoid constraining the inputs and outputs) - I think it would be ok. what do you think?  --- Quote End ---    Hi,  you can set a default delay:    define input_delay -default 1.00 -ref {clkb:r}  When you import the netlist and you run a "simple" P&R run Quartus will not move your register. In case you use register retiming in Quartus the registers maybe will be moved, but Quartus will take care of the timing.   BTW: Did you check your reset and clock connectivity ?   Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,  you can set a default delay:    define input_delay -default 1.00 -ref {clkb:r}  When you import the netlist and you run a "simple" P&R run Quartus will not move your register. In case you use register retiming in Quartus the registers maybe will be moved, but Quartus will take care of the timing.   BTW: Did you check your reset and clock connectivity ?   Kind regards  GPK  --- Quote End ---    ok - I'll try it. and I did check the connectivity.  thanks!