Device tree generation for Agilex SoC

[Mikhail_a]

Hello!

Is there any way I can generate a device tree for Yocto when building it for Agilex device? I know that for older devices there was a Device Tree Generator, but I see that it is marked as obsolete. So am I really have to all the work manually? To be honest it would be a bit confusing as other vendors have automatic device tree assembler tools. But anyways if yes, then do you have any adequate example how to create a device tree entrance for:

1) custom IP

2) standard Intel IPs from Platform Designer?

Both IP types are connected to SoC via FPGA2HPS or HPS2FPGA briges.

The guide from rocketboards ( https://www.rocketboards.org/foswiki/Documentation/HOWTOCreateADevicetreeForAgilexSoC ) looks very unclear.

Thank you in advance.

[aikeu]

Hi retsd,

The building bootloader(GSRD reference) from the link below will show the source being used to build u-boot and linux kernel:

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderAgilex7

The same source can be found in opensource link for u-boot-socfpga and linux-socfpga:

https://github.com/altera-opensource

The device tree node enablement for the working GSRD can be searched with "Go to file" and type socfpga_agilex(for your case)

Based on the defaut working GSRD device tree declaration, I will use it as a reference if I will need to add/consider any component changes in the system.

The basic idea to consider a component in the device tree is to know the address being used in the system.

The address will refer to the HPS memory map, for your case will be agilex from the link below:

https://www.intel.com/content/www/us/en/programmable/hps/agilex/hps.html

Example if I would like to use HPS UART1 for logging and I will refer to the default working HPS UART0 to add/modify the device tree accordingly in order to add/consider HPS UART1.

Example if I would like to add an IP to the HPS bridge, I will refer to the HPS memory map and check the start address of the particular bridge and knowing the address offset of the IP connected to the HPS bridge in the hardware design in order to identify the address to be defined in the device tree node. The hardware design address connections can be checked with Quartus platform designer.

It will be easier to have a working reference as an example to add/modify a device tree node. Therefore I suggest the working GSRD example as above. I never build yocto before when making changes to the device tree and I am not sure does it really required for certain specific component. I was using the rootfs prebuild image as part of the building bootloader process from the link as below:

https://releases.rocketboards.org/

For further device tree node information:

https://elinux.org/Device_Tree_Usage

Thanks.

Regards,

Aik Eu

[aikeu]

Hi retsd,

Do let me know if you required more information.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi retsd,

I will close this thread if no further question.

Thanks.

Regards,

Aik Eu

[Mikhail_a]

Hello Aik Eu

You can close that thread as it seems I was able to do things I needed. 

Thank you.

[aikeu]

Hi retsd,

Ok great. I will close this thread for now.

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

Thanks.

Regards,

Aik Eu