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I cannot build cyclone V SPL using LPDDR2 with EDS 19.1.
Does U-boot socfpga_v2019.04 really support LPDDR2?
Longer version:
I have a custom cyclone V board with LPDDR2 HPS memory and so far
I've been using SPL based on U-boot branch socfpga_v2013.01.01.
According to:
https://rocketboards.org/foswiki/Documentation/BuildingBootloader#Cyclone_V_SoC_45_Boot_from_SD_Card
it seems that I have to upgrade U-boot to socfpga_v2019.04 when using EDS 19.1
but SPL does not compile when using LPDDR2 HPS memory due to missing defines.
The missing ones all seem to be related to DDR3 (e.g. RW_MGR_MRS1).
I tried building new projects containing nothing but a HPS block:
When using default SDRAM (DDR3), SPL builds fine. The defines my build was
missing all exist in hps_isw_handoff/*/sequencer_auto.h
When using Micron LPDDR2 SDRAM, SPL does not build due to missing defines.
hps_isw_handoff/*/sequencer_auto.h does not contain the missing defines.
See build log below.
Looking at code in u-boot-socfpga/drivers/ddr/altera I find no evidence
of LPDDR2 support, e.g. LPDDRDIS is hardcoded to '1' in sequencer.c
So it seems that socfpga_v2019.04 does not support LPDDR2?
/Thomas
k7:~/altera/pl/c5_test_lpddr2/software/bootloader/u-boot-socfpga$ make -j8
CHK include/config/uboot.release
CHK include/generated/timestamp_autogenerated.h
UPD include/generated/timestamp_autogenerated.h
CHK include/generated/version_autogenerated.h
CHK include/generated/generic-asm-offsets.h
CHK include/generated/asm-offsets.h
HOSTCC tools/mkenvimage.o
HOSTCC tools/fit_image.o
HOSTCC tools/image-host.o
HOSTCC tools/dumpimage.o
HOSTCC tools/mkimage.o
HOSTLD tools/mkenvimage
HOSTLD tools/dumpimage
HOSTLD tools/mkimage
CC arch/arm/mach-socfpga/wrap_pll_config.o
CC common/main.o
CC cmd/version.o
LD arch/arm/mach-socfpga/built-in.o
LD common/built-in.o
LD cmd/built-in.o
CC lib/smbios.o
CC lib/display_options.o
CC lib/efi_loader/helloworld.o
CC lib/efi_loader/efi_reloc.o
CC lib/efi_loader/efi_freestanding.o
LD lib/efi_loader/helloworld_efi.so
OBJCOPY lib/efi_loader/helloworld.efi
LD lib/built-in.o
LD u-boot
OBJCOPY u-boot.srec
OBJCOPY u-boot-nodtb.bin
SYM u-boot.sym
CAT u-boot-dtb.bin
COPY u-boot.bin
MKIMAGE u-boot.img
MKIMAGE u-boot-dtb.img
CC spl/common/spl/spl.o
CC spl/arch/arm/mach-socfpga/wrap_pll_config.o
CC spl/arch/arm/mach-socfpga/wrap_iocsr_config.o
CC spl/arch/arm/mach-socfpga/wrap_pinmux_config.o
CC spl/arch/arm/mach-socfpga/wrap_sdram_config.o
CC spl/lib/display_options.o
arch/arm/mach-socfpga/wrap_sdram_config.c:205:25: error: ‘RW_MGR_INIT_RESET_0_CKE_0’ undeclared here (not in a function); did you mean ‘RW_MGR_ACTIVATE_0_AND_1’?
.init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0,
^~~~~~~~~~~~~~~~~~~~~~~~~
RW_MGR_ACTIVATE_0_AND_1
arch/arm/mach-socfpga/wrap_sdram_config.c:206:25: error: ‘RW_MGR_INIT_RESET_1_CKE_0’ undeclared here (not in a function); did you mean ‘RW_MGR_INIT_RESET_0_CKE_0’?
.init_reset_1_cke_0 = RW_MGR_INIT_RESET_1_CKE_0,
^~~~~~~~~~~~~~~~~~~~~~~~~
RW_MGR_INIT_RESET_0_CKE_0
arch/arm/mach-socfpga/wrap_sdram_config.c:219:22: error: ‘RW_MGR_MRS0_DLL_RESET’ undeclared here (not in a function); did you mean ‘RW_MGR_SGLE_READ’?
.mrs0_dll_reset = RW_MGR_MRS0_DLL_RESET,
^~~~~~~~~~~~~~~~~~~~~
RW_MGR_SGLE_READ
arch/arm/mach-socfpga/wrap_sdram_config.c:220:26: error: ‘RW_MGR_MRS0_DLL_RESET_MIRR’ undeclared here (not in a function); did you mean ‘RW_MGR_MRS0_DLL_RESET’?
.mrs0_dll_reset_mirr = RW_MGR_MRS0_DLL_RESET_MIRR,
^~~~~~~~~~~~~~~~~~~~~~~~~~
RW_MGR_MRS0_DLL_RESET
arch/arm/mach-socfpga/wrap_sdram_config.c:221:17: error: ‘RW_MGR_MRS0_USER’ undeclared here (not in a function); did you mean ‘RW_MGR_MRS0_DLL_RESET’?
.mrs0_user = RW_MGR_MRS0_USER,
^~~~~~~~~~~~~~~~
RW_MGR_MRS0_DLL_RESET
arch/arm/mach-socfpga/wrap_sdram_config.c:222:22: error: ‘RW_MGR_MRS0_USER_MIRR’ undeclared here (not in a function); did you mean ‘RW_MGR_MRS0_USER’?
.mrs0_user_mirr = RW_MGR_MRS0_USER_MIRR,
^~~~~~~~~~~~~~~~~~~~~
RW_MGR_MRS0_USER
arch/arm/mach-socfpga/wrap_sdram_config.c:223:13: error: ‘RW_MGR_MRS1’ undeclared here (not in a function); did you mean ‘RW_MGR_IDLE’?
.mrs1 = RW_MGR_MRS1,
^~~~~~~~~~~
RW_MGR_IDLE
arch/arm/mach-socfpga/wrap_sdram_config.c:224:17: error: ‘RW_MGR_MRS1_MIRR’ undeclared here (not in a function); did you mean ‘RW_MGR_MRS0_USER’?
.mrs1_mirr = RW_MGR_MRS1_MIRR,
^~~~~~~~~~~~~~~~
RW_MGR_MRS0_USER
arch/arm/mach-socfpga/wrap_sdram_config.c:225:13: error: ‘RW_MGR_MRS2’ undeclared here (not in a function); did you mean ‘RW_MGR_MRS1’?
.mrs2 = RW_MGR_MRS2,
^~~~~~~~~~~
RW_MGR_MRS1
arch/arm/mach-socfpga/wrap_sdram_config.c:226:17: error: ‘RW_MGR_MRS2_MIRR’ undeclared here (not in a function); did you mean ‘RW_MGR_MRS1_MIRR’?
.mrs2_mirr = RW_MGR_MRS2_MIRR,
^~~~~~~~~~~~~~~~
RW_MGR_MRS1_MIRR
arch/arm/mach-socfpga/wrap_sdram_config.c:227:13: error: ‘RW_MGR_MRS3’ undeclared here (not in a function); did you mean ‘RW_MGR_MRS2’?
.mrs3 = RW_MGR_MRS3,
^~~~~~~~~~~
RW_MGR_MRS2
arch/arm/mach-socfpga/wrap_sdram_config.c:228:17: error: ‘RW_MGR_MRS3_MIRR’ undeclared here (not in a function); did you mean ‘RW_MGR_MRS2_MIRR’?
.mrs3_mirr = RW_MGR_MRS3_MIRR,
^~~~~~~~~~~~~~~~
RW_MGR_MRS2_MIRR
arch/arm/mach-socfpga/wrap_sdram_config.c:234:15: error: ‘RW_MGR_RETURN’ undeclared here (not in a function); did you mean ‘RW_MGR_MRS3’?
.rreturn = RW_MGR_RETURN,
^~~~~~~~~~~~~
RW_MGR_MRS3
arch/arm/mach-socfpga/wrap_sdram_config.c:236:13: error: ‘RW_MGR_ZQCL’ undeclared here (not in a function); did you mean ‘RW_MGR_MRS3’?
.zqcl = RW_MGR_ZQCL,
^~~~~~~~~~~
RW_MGR_MRS3
scripts/Makefile.build:278: recipe for target 'spl/arch/arm/mach-socfpga/wrap_sdram_config.o' failed
make[2]: *** [spl/arch/arm/mach-socfpga/wrap_sdram_config.o] Error 1
scripts/Makefile.spl:398: recipe for target 'spl/arch/arm/mach-socfpga' failed
make[1]: *** [spl/arch/arm/mach-socfpga] Error 2
make[1]: *** Waiting for unfinished jobs....
LD spl/common/spl/built-in.o
LD spl/lib/built-in.o
Makefile:1664: recipe for target 'spl/u-boot-spl' failed
make: *** [spl/u-boot-spl] Error 2
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Hello,
Kindly make sure to follow the steps here:
https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2019.04/doc/README.socfpga
This will generate the handoff files. Hardware wise it should be supported. Uboot wise, I will check with our internal engineering to confirm if 2019.04 supports LPDDR2
Thank you
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Hi,
I've been using the work flow described in README.socfpga and also on https://rocketboards.org/foswiki/Documentation/BuildingBootloader
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So have You figured out whether the lpddr2 is suported?
I'm trying to build spl for project generated in q20.1 with CycV and LPDDR2 but have very simmilar compile time errors.
Should I use q18.1 for this?
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@Fawaz_Al-Jubori, has Intel stopped supporting LPDDR2?
Which Quartus and SoCEDS version should I use to build the bootloaders for the board with LPDDR2?
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One more thing, can you try to create uboot using 18.1? this will use older uboot version.
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If I build the project using Quartus 19.1 but use EDS 18.1 (and U-boot socfpga_v2013.01.01 ) when creating BSP
and building SPL/U-boot, SPL builds (and boots) just fine.
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