FPGA clock frequency

[hasssanadeli]

Hello,

To program the FPGA of MitySom-5CSX, I was wondering if could anyone tell me the FPGA clock frequency pin number and its value. I tried 50MHz and AA8 pin number but it did not work.

Thanks,

[Nurina]

Hello,

What do you mean it did not work? How did you set the clock frequency and how did you check for it?

Regards,

Nurina

[hasssanadeli]

Hello Nurina,

Thanks for your response. We are using MATLAB HDL coder to generate VHDL codes and synthesis and analysis of FPGA. In one step in the target platform, we need to assign the clock frequency port and its value. When I run it I face this error:

" Error (175019): Illegal constraint of I/O pad to the location PIN_AA8
Info (14596): Information about the failing component(s):
Info (175028): The I/O pad name(s): CLKIN
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (169094): Can't place pin CLKIN at location AA8 (PAD_50) because that location is a dedicated programming pin location (1 location affected) File: PIN_AA8"

Thanks,

Hassan

[FvM]

Hi,
where did you get the idea to use pin AA8 as clock input? I presume your board has a user manual telling which pins are wired to a clock source to be used as FPGA clock. If not, there's a Cyclone V pinout file, also Quartus pin planner gives the information. I checked pinout file and found that AA8 is configuration DCLK, surely not suited as FPGA clock input.

[hasssanadeli]

Hi, thanks for your response I checked the datasheet but unlike the other FPGA devices I used before this controller is more complicated and I could not exactly find out which pin is related to the FPGA clock.

[Nurina]

Hi Hassan,

I would just remove the pin location and let Quartus choose the pin itself.

Regards,

Nurina

[hasssanadeli]

Thanks Nurina, 

Thanks for your response. I ran the VHDL codes but when I go to the pin assignments I can just find the manual assignment. Could you please let me know where can I find this auto-assign option?

Thanks,

Hassan

[FvM]

Hi,

letting Quartus select a clock has the disadvantage that Quartus knows nothing about MitySOM-5CSX SoC module and which FPGA clock pins are exposed to the module connector. You want to review datasheet or design guide to learn about available clock inputs.

Datasheet reveals that all global clock pins except clk4 p/n and clk5 p/n  are available, to gether with respective FPGA and module pin number.

Intended usage of FPGA IO banks in your application probably results in preferences for clock pin selection.

[Nurina]

Hi,

You just need to remove the pin assignment. During compilation Quartus will auto-assign it for you.

However I do agree with above comment, you should refer to the data sheet from your devkit for the suggested pin.

May I know which OPN you are using?

Regards,

Nurina

[hasssanadeli]

Hi Nurina, thanks for your response. I am using MitySom5CSX controller board (https://www.criticallink.com/product/mitysom-5csx/) integrated with 5CSXFC6C6U23I7N. 

[Nurina]

Hi Hassan,

Why don't you try pin V11 or V12? These are CLK0 p and CLK1 p respectively.

Here is the Cyclone V SX device pin out: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-v/5csxfc6.pdf

And here is MitySOM-5CSx pin out: https://www.criticallink.com/wp-content/uploads/MitySOM-5CSx-Datasheet.pdf#page=14

Regards,

Nurina

[Nurina]

Hi Hassan,

Any updates?

[hasssanadeli]

Hi Nurina, 

I have this controller (https://www.criticallink.com/product/mitysom-5csx/ ) board on my project board and also I have this development kit with the same controller (https://www.criticallink.com/product/mitysom-5csx-dev-kit/). 

I tried the Y13 pin with 100MHz for clock frequency. It is working now on the development kit and output is what I expected. However, when I download the same file on the controller itself, in the signal tap logic analyzer I am facing the status of "Waiting for Clock" strangely. In our project board, I powered the circuit with 5V and 3.3V to the corresponding pins. I am assuming the clock frequency is provided internally. 

Do you have any idea about this issue? 

Thanks,

Hassan

[Nurina]

Hi Hassan,

I think there's something wrong with your signal tap nodes. Try running a new compilation and generate new .sof file for your controller.

Regards,

Nurina

[Nurina]

Any updates?

Regards,

Nurina

[Nurina]

Hi,

We have not received a reply from you. As such, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Best regards,

Nurina

[hasssanadeli]

Hi Nurina, 

Thanks for your support. The programming procedure and assignment are fine. I found out the oscillator is not provided for Y13 on the FPGA module itself, and on the development kit they mount it separately from the FPGA module as external. I tried different oscillators that are provided for other banks to provide it internally. I still facing the "waiting for clock" status. I was wondering if you could please check if is there anything else like any reset or configuration selection should I enable first to use those oscillators.

Thanks,