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Hi,
In the past a few days, I have been debugging the system in Cyclone 10 LP 10CL120YF484.
I did the following steps:
1) In Platform Designer, I create a new IP whose name BF5V whose interface is AXI4Lite. Please see the following picture.
2) I convert Avalon to AXI4Lite. please see the picture below.
3) in C code, I try to control ADC and etc, and I can control them successfully. however, If I use the following C code to write Avalon bus, the data in S_AXI_AWDATA is not as expected. For example, I write 0x55AA, 0x33, 0x0001, 0x4000 to the bus, but the data on S_AXI_AWDATA is 0x55AA, 0x33, 0x4000. The data 0x0001 is missing.
in addition, the AXI4 Lite interface in my IP has been previously used in our project successfully.
Is there any doc about how to convert Avalon to AXI4Lite?
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Responded in your original post.
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Hi
Could you share what is the define for the FPGA_SCAN_WRITE, FPGA_SCAN_WDATA and FPGA_SCAN_WADDR?
Regards
Jingyang, Teh
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Thank you!
As @sstrell responded in my original thread, I posted all information in my original post. please see the last post in my original thread in the following link.
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Hi
Is it possible if you could use the macro available in the io.h of the Nios HAL?
Try using the IOWR macros to write the values.
Just for further checking, could you send me a screenshot of the address map in the platform designer?
Regards
Jingyang, Teh
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Hi
Did you try out the suggestion in the previous comment?
Regards
Jingyang, Teh
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Hi
As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Regards
Jingyang, Teh

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