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arria V compiler and hwlibs

bsp_user
Beginner
3,861 Views

Hi,

My goal is to successfully build and run a bare-metal app which measure time by reading one of the the Arria V Soc HPS timers using hwlib. Afterwards I wish to use the same app on a custom board which contains the same HPS as the Arria V SoC. 

I'm using Windows with Arm DS-5 v5.29.1 and IntelFPGA suite 18.1 (these the packages I have license for)

 

I tried to follow several examples like here:

https://www.intel.com/content/www/us/en/docs/programmable/683211/current/bare-metal-user-guide.html

but got some conflicts when using different compilers. 

 

I have two questions please:

1. I don't know which compiler is best for me. I got lost between the following three options:

1.1. In the Bare Metal user guide (link above) they suggest using the ARM Compiler 5 C.

1.2. In the HWlib section, they refer to git repository which recommend using the Linaro suite.

1.3. In the Altera-SoCFPGA-HardwareLib-Timer-AV-ARMCC example (intelFPGA 18.1 version) they use , by defualt , the GCC 4.x [arm-linux-gnueabihf](DS-5 built in) and if I switch to the ARM CC 5 as the Bare Metal user guide suggests I get "program -E" error.

So I got a little confused regarding which one to use and why. 

 

2. The official Intel HWLib source is here:

https://github.com/altera-opensource/intel-socfpga-hwlib

they have a category for av/cv but inside all the examples are for cyclone V only (no av examples)

is there any guide regarding how to configure a new "hello" app to use the hwlib? 

- do I need to compile the hwlib first? 

- if do, does it generates libraries for inclusion in my "hello" app?

 

 

Thanks

 

 

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1 Solution
EBERLAZARE_I_Intel
3,296 Views

Hi,


Since the case have been open for too long, we recommend that we close the thread as per our support procedure.


However, I highly recommend that you open issues that you'd face separately, for e.g your help needed for Quartus compilation on another then the Baremetal build on next.


Once you open the new case/s, we will support your issue then. Hopes this helps.


View solution in original post

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27 Replies
EBERLAZARE_I_Intel
3,120 Views

Hi,


I hope I can answer both. You can get the:

https://github.com/altera-opensource/intel-socfpga-hwlib/tree/master/examples/CVAV/Altera-SoCFPGA-HelloWorld-Baremetal-ARMCC


And build it as instructed in the readme. Installation such as linaro, go to the main page and follow the steps there.


The Cyclone V SoC and Arria V SoC are almost identical. Unfortunately Arria V SoC have reached EOL, but you may still use this design and use it for your device.


For the hello world, device dependencies are in the scatter file.



p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


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EBERLAZARE_I_Intel
3,085 Views

Hi,


I think your comment did not went through.


Do you have any further questions?


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bsp_user
Beginner
3,057 Views

I apologies for that.

 

Yes I encountered several issues during my baremetal "hello world" compilation and loading it on the dev board. 

Can I ask regarding these issues here or open a new thread?

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EBERLAZARE_I_Intel
3,043 Views

Hi,


Yes, if you have errors it would be helpful if you have screenshots along with the text logs.


What is the latest issue that you are facing?


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EBERLAZARE_I_Intel
3,028 Views

Hi,


Can you check my previous comments?


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bsp_user
Beginner
3,015 Views

Hi, 

Sorry for the late response.  I tried to gather images for this question.

 

My goal is to build my own bare metal app which being loaded from qspi into sdram by preloader and uses HWLib.

my problem is that only the preloader is loaded from qspi and not my app.

These are the steps I've taken so far:

 

1.  Create a project for HWLib and a seperate "hello" project which uses the HWLib.

- I created my project using Arm compiler 5 (DS built in) and

the instructions from section 1.6.1.1:

 https://www.intel.com/content/www/us/en/docs/programmable/683211/current/create-project-22401.html

- I use the same scatter file as appears in section 1.6.3.1 (the upper one):

https://www.intel.com/content/www/us/en/docs/programmable/683211/current/create-a-new-scatter-file-to-locate.html

- The projects is compiles succesuflly and .bin is generated from .axf using fromelf.

- 1.PNG - 4.PNG shows some of the settings and compilaion output

 

2. After the app .bin file is ready I used the following mkimage  command to add header for my .bin app:

mkimage -A arm -O u-boot -T standaone -C none -a 0x02000000 -e 0x02000000 -n "alg_baremetal" -d alg.bin alg.img

- 5.PNG

 

3. I created and compiled the preloader and flashed both preloader and alg.img using instructions

from:

https://www.intel.com/content/www/us/en/docs/programmable/683265/current/booting-from-qspi-flash.html

- I used the handoff folder for generating the BSP and preloader from here:

https://www.rocketboards.org/foswiki/Documentation/WS1IntroToAlteraSoCDevices

(the ALTERA AV SOC files)

- flashed alg.img and not alg.bin

- 6.PNG for flashing alg.img

 

4. boot log:

[15:29:51:390] U-Boot SPL 2013.01.01 (Mar 02 2023 - 16:50:19)␍␊

[15:29:51:390] BOARD : Altera SOCFPGA Arria V Board␍␊

[15:29:51:390] CLOCK: EOSC1 clock 25000 KHz␍␊

[15:29:51:390] CLOCK: EOSC2 clock 25000 KHz␍␊

[15:29:51:390] CLOCK: F2S_SDR_REF clock 0 KHz␍␊

[15:29:51:390] CLOCK: F2S_PER_REF clock 0 KHz␍␊

[15:29:51:390] CLOCK: MPU clock 1050 MHz␍␊

[15:29:51:390] CLOCK: DDR clock 533 MHz␍␊

[15:29:51:390] CLOCK: UART clock 100000 KHz␍␊

[15:29:51:390] CLOCK: MMC clock 50000 KHz␍␊

[15:29:51:390] CLOCK: QSPI clock 350000 KHz␍␊

[15:29:51:390] RESET: COLD␍␊

[15:29:51:390] SDRAM: Initializing MMR registers␍␊

[15:29:51:390] SDRAM: Calibrating PHY␍␊

[15:29:51:390] SEQ.C: Preparing to start memory calibration␍␊

[15:29:51:417] SEQ.C: CALIBRATION PASSED␍␊

[15:29:51:417] SDRAM: 1024 MiB␍␊

[15:29:51:417] SDRAM: Initializing SDRAM ECC␍␊

[15:29:52:872] SDRAM: ECC initialized successfully with 1464 ms␍␊

[15:29:52:872] SDRAM: ECC Enabled␍␊

[15:29:52:898] SF: Read data capture delay calibrated to 3 (0 - 7)␍␊

[15:29:52:898] SF: Detected N25Q512 with page size 65536, total: 67108864␍␊

 

 

Thank you very much for your patience.

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EBERLAZARE_I_Intel
2,991 Views

Hi,


Thanks, I shall look into it, allow me some time to get back to you thanks.


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EBERLAZARE_I_Intel
2,965 Views

Hi,


For preloader + hello world, I have the steps that I did on our Cyclone V SoC dev kit flashed to the QSPI.


I will try to find and provide to you.


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bsp_user
Beginner
2,950 Views

I appreciate it.

I don't know how to debug the problem.

 

 

1. Can I change the preloader startup prints? (this way I'll know I'm using the latest version after modifying it)

2. Does this problem can relate to scatter file?

3. Can I debug the exact process of the preloader, see which address it tries to load and figure if my app is indeed flashed there? 

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EBERLAZARE_I_Intel
2,939 Views

Hi,


For Cyclone V SoC Baremetal, hwlib + QSPI with U-boot SPL, the files required are:

  • U-boot-spl.sfp
  • application.img


We use the latest building bootloader to get the U-boot file all the way from Quartus up to Configure and build U-Boot:

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Cyclone_V_SoC_45_Boot_from_QSPI


Then, get HWLib and install the toolchain:

cd $TOP_FOLDER

git clone https://github.com/altera-opensource/intel-socfpga-hwlib

cd intel-socfpga-hwlib/tools

./install_linaro.sh

export PATH=`pwd`/gcc/bin:$PATH


#Reference:

https://www.rocketboards.org/foswiki/Documentation/HWLib#Installation


Build the application:

cd $TOP_FOLDER

cd intel-socfpga-hwlib/examples/CVAV/Altera-SoCFPGA-HardwareLib-Timer-CV-GNU/

# build once to bring hwlibs code

make SEMIHOSTED=0 MEMORY=ddr

# cleanmake

make clean

# change hwlibs link address to match what U-Boot wants

sed -i 's/0x00100040/0x01000040/g' hwlib/src/linkerscripts/cvav-ddr.ld

# move stack out of the way just in case

sed -i 's/0x80000/0x00200000/g' hwlib/src/linkerscripts/cvav-ddr.ld

# build again with the new address

make SEMIHOSTED=0 MEMORY=ddr

# create binary file

arm-eabi-objcopy -O binary application.elf application.bin

# create img file

$TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/tools/

mkimage -A arm -T standalone -C none -a 0x01000040 -e 0x01000040 -n "bare-metal image" -d application.bin application.img


Build the QSPI image to be flash:

cd $TOP_FOLDER

cat cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/spl/u-boot-splx4.sfp \

   intel-socfpga-hwlib/examples/CVAV/Altera-SoCFPGA-HardwareLib-Timer-CV-GNU/application.img \

> qspi-image.bin




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bsp_user
Beginner
2,934 Views

Thank you for your reply.

I use different components than yours:

1. I'm building everything in Windows using SoC EDS suite and ARM DS-5.

2. I'm using ARM compiler 5 (not GNU)

3. I'm building bare metal app and not a Linux app.

 

The reason is that I don't have a license for ARM DS-5 for linux.

 

Can you help me with my problem in my environment?

 

 

Thanks

 

 

 

 

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EBERLAZARE_I_Intel
2,920 Views

Hi,


Anyway, please pin the steps I've given, it will be useful for reference point of view.


One question, for QSPI would you want something like a U-boot SPL to show some logs. The build is to get the U-boot SPL binary, and stop after finishing the U-boot steps not Linux.


If you just want it to work on the ARM debugger you need the application.axf to be loaded from ARM DS.


I have not tried personally on Windows, it is best if you have a virtual machine and get Ubuntu 20.04 >, if you proceed on Windows you need to make sure you have install linaro:

https://www.rocketboards.org/foswiki/Documentation/SoCEDS#Install_Linaro_Bare_45metal_AN1


It should be similar as in DS-5, the flow should see something like this:

https://www.rocketboards.org/foswiki/Documentation/SoCEDS#Cyclone_V_Bare_Metal_Example_Using_SoC_EDS_Standard_Edition


You still need to build the U-boot. Please check the above flow, and let me know which steps are you having issues with based on the above steps.


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EBERLAZARE_I_Intel
2,880 Views

Hi,


Do you have any new update?


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bsp_user
Beginner
2,868 Views

I'll pin it.

I think there is a little mess so by your permission I'll start from the beginning.

 

1. OS:

I see that you recommend on Ubuntu (and other guides as well). 

Can I  create and compile my baremetal app and preloader on a non licenced version of Quartus, ARM DS5 and EDS SoC suite (free versions)?

I'm asking that because maybe it will be easier if I use the same OS as you do.

 

2. Compiler:

I see that you recommend on linaro (gcc) and not ARM v5 compiler.

I'll try that. I remember it caused me some problems with HWLib but we will figure it out later.

 

3. Preloader:

You are right. I wish to use the preloader only without additional bootloader stage afterwards and before the baremetal app. I just wish it to print some uniqe string during its startup for me to recognize its indeed the preloader I built.

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EBERLAZARE_I_Intel
2,825 Views

Hi,


For the SoC EDS you can install the Standard free version on the Ubuntu machine, from my experience, it was all fresh install from Ubuntu 20.04 to the SoC EDS, but with already compiled Quartus project and bring over the "handoff" files needed then proceed OK:


After installing the virtual machine I had ran the following commands to make sure I have all the packages I need:

 

$ sudo apt-get update

$ sudo apt-get install openssh-server mc libgmp3-dev libmpc-dev gawk wget git diffstat unzip texinfo gcc build-essential chrpath socat cpio python3 python3-pip python3-pexpect xz-utils debianutils iputils-ping python3-git python3-jinja2 libegl1-mesa libsdl1.2-dev pylint3 xterm python3-subunit mesa-common-dev zstd liblz4-tool git fakeroot build-essential ncurses-dev xz-utils libssl-dev bc flex libelf-dev bison  xinetd tftpd tftp nfs-kernel-server libncurses5 libc6-i386 libstdc++6:i386 libgcc++1:i386 lib32z1 device-tree-compiler curl mtd-utils u-boot-tools net-tools swig doxygen -y


I guess I'll keep the case open for few days for you to have your tests.


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EBERLAZARE_I_Intel
2,771 Views

Hi,


Any update on your new testings?


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bsp_user
Beginner
2,718 Views

Hi,

I've download the following tools for Ubuntu 18.04 (I use it for other projects and its easier for me instead of installing 20.04):

- ARM DS:              DS000-BN-00001-r22p2-00rel0.tgz

- Quartus Prime:  Quartus-22.1std.1.917-linux-complete.tar

- SoCEDS:              SoCEDSSetup-20.1.0.711-linux.run

- HWlibs

 

I started to follow your guides and now I'm stuck at:

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10?elq_cid=3780821_ts1679915029555&erpm_id=6664898_ts1679915029555#Cyclone_V_SoC_45_Boot_from_QSPI

 

instruction:

~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
make generate_from_tcl

 

bsp@bsplinux1:~/Desktop/cv_example.qspi/cv_soc_devkit_ghrd$ ~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
> make generate_from_tcl
make -s scrub_clean
You're already as clean as it gets!
make quartus_generate_qsf_qpf quartus_generate_top qsys_generate_qsys
make[1]: Entering directory '/home/bsp/Desktop/cv_example.qspi/cv_soc_devkit_ghrd'
rm -rf soc_system.qsf soc_system.qpf
quartus_sh --script=create_ghrd_quartus.tcl
quartus_sh: error while loading shared libraries: libprotobuf.so.14: cannot open shared object file: No such file or directory
Makefile:347: recipe for target 'quartus_generate_qsf_qpf' failed
make[1]: *** [quartus_generate_qsf_qpf] Error 127
make[1]: Leaving directory '/home/bsp/Desktop/cv_example.qspi/cv_soc_devkit_ghrd'
Makefile:386: recipe for target 'generate_from_tcl' failed
make: *** [generate_from_tcl] Error 2

 

 

so it looks for a missing shared library

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EBERLAZARE_I_Intel
2,714 Views

Hi,


Can you open the Quartus project in GUI and compile manually?


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