could not create the verilog HDL file

[Aravindpb]

i am using the altera 5CGXFC7C62317N , when try to create the verilog HDL file

quartus showing some error like(Error (275069): Design file contains illegal characters for Verilog HDL) i dont know what to do .

please let me know if u have solution

[Vicky1]

Hi Aravind,

Could you please provide bit more information?

Quartus version(lite/pro/std) & Device used.

what exactly you did? please provide the Full screenshot.

Thanks,

Vikas

[Aravindpb]

hai vicky thanks for your valuable reply you asked some more information needed . i provide the details and snap of my project error what is appering in the screen in the below content

using cyclone v 5CGXFC7C6F2317 family

compiler quartus prime 16.0 lite edition

snapshots of my projects

these are steps i followed to create verolg HDL

Thanks,

Aravind p

[Abe]

Were you able to create a Quartus project for the Cyclone V GX chip? Do you get this error when running the Quartus flow ?

The error states that the design file you created has illegal characters. Can you post the code here so that we can check it.?

Are you creating the design using the Block diagram edit BDF file. If so, delete the existing .v files, and then try compiling again. You could also try a clean of the project via the Project menu -> Clean Project.

[Aravindpb]

Hai Abe

Thank you for your reply as per your instruction tried the points what you tell in previous msg but the thinks are getting again error

I created the design using the Block diagram edit BDF file and also deleted the existing .v file and tried once again also but the same error is appering as well as cleared my project via project menu-> clean project same error is appering on the screen

for more information i have provided screenshots in below plz go through my snaps

let me know the solutions

Thanks ,

Aravind p

[Aravindpb]

Hai frdz thank you for your valuable reply , you two asked some more information about my questions . i provided detail asked in the below

using cyclone v 5CGXFC7C6F2317 family

compiler quartus prime 16.0 lite edition

I created the design using the Block diagram edit BDF file and also deleted the existing .v file and tried once again also but the same error is appering as well as cleared my project via project menu-> clean project same error is appering on the screen

for more information i provided my screen shorts what are the error appering

plz go through this screen shot let me know the solution

[Abe]

Why do you need to convert the BDF to Verilog? Does the project compile (Analysis, Elaborate, Fitter , TIming Analysis) without errors? From the screenshots it looks like the compile process goes through.

Can you archive the project and upload it here so that we can take a look. Can't find out the cause of the issue from the screenshots. Have you tried checking the generated verilog files to see if there are any illegal characters? Can you post the Verilog files here?

[Aravindpb]

hai abe

problem is due to confidential i can't share any files to outside

project compiled sucessfully point which you added in the above there is no problem in compilation

facing this problem since two days plz let me know the solution abe

Thanks

Aravind p

[Vicky1]

Hi Aravind,

It is difficult to support without looking the design, if you want share the project archive only with us(Abe & Vicky) you can use "My Messages" option from your profile.

At least you should provide the log file(Select "All" from Messages window & copy the whole content in word/text file)

Regards,

Vikas