AXI4 DMA Master Error

[Manprocoder]

Hi expert,

I am building SoC system that includes components as follows:

+ CPU

+ onchip_memory_2_0

+ onchip_memory_2_1 (source address)

+ onchip_memory_2_2 (destination address)

+ IP (Active Ascon) has AXI4 DMAC 

As program runs at simulation mode,  read burst request runs well, but write burst always encounters problem (awready is always "0" logic level), so DMAC always wait slave, leading 

my system to be stuck.

Could you clarify it to me? Thanks you so much.

Attached image

[ScottW_Altera]

Hi @Manprocoder,

Could you provide some more details such as Quartus version and board/platform you are building for?

Thanks.

[Manprocoder]

Hi,
I provide some additionals as follows:
+ quartus lite 18.1
+ board De10 standard (5CSXFC6D6F31C6)

[Manprocoder]

Hi experts,

I provide additional details (waveform and C code) to facilitate your supports.

+Quartus Version: Quartus Prime Lite 18.1

+Board: 5CSXFC6D6F31C6 (DE10 Standard)

As I mentioned READ BURST request runs well (handshake arvalid & arready)

Read Waveform:

But WRITE BURST request always encounter problem (no handshake awvalid & awready)

Write Waveform:

C code program:

[ScottW_Altera]

Thanks for the details @Manprocoder.

From what I can see the platform design looks OK and the NIOS appears to be doing what it should to initialize the DMA so I would conclude the problem is likely to be with the active_ascon IP. I will see if I can get someone from the AXI team to take a look and give some guidance. It will likely require sharing more information about the active_ascon IP block.

[Manprocoder]

Hi @Scot 

I provide overall details about active_ascon IP 

Allow me to mention my issue again: WRITE BURST is being refused by slave (onchip_memory2_2)

1. Block Diagram

* Function of partial blocks

 + RD_CRF: store config (DMAC config + ASCON config) read from source memory and generate info for WR_REQUEST block

+ STORE_CKN_AD: store those data such as: ascon config, KEY, NONCE, AD, TEXT, TAG (using fifo)

+ FORMAT_DATA: format data read from source memory to run ASCON function (ASCON is algorithm that includes AEAD & HASH)

+ other remaining blocks: function is clearly presented through their name.

2. Data Frame & Timing Diagram

- Data frame (stored in source memory)

- Timing Diagram

3. WR REQUEST BLOCK

- WR_BURST GENERATOR RTL CODE

*Note: I only use information as follows

+ size: 3'b010 (always write 1 word (4 bytes) each transfer)

+ burst: 2'b01 (only use INCR burst)

[Manprocoder]

Allow me to update WR_REQUEST block.

Exact block I am using below:

[Manprocoder]

Hi @ScottW_Altera 

I provide additional details on signals of active_ascon IP in platform designer.

- System with Platform Designer Interconnect

[ScottW_Altera]

Thank you for the comprehensive overview of the IP in question @Manprocoder 

I am trying to find you some help internally as this isn't my area of expertise and nothing is jumping out at me from what you have posted. Hopefully others in the community may also be able to offer some advice.

Seems obvious but I will ask anyway. I am assuming the onchip memory is configured as RAM and not ROM?

[Manprocoder]

Thanks for your attention @ScottW_Altera 

My problem is too hard for me to address it, and now, I'm totally beat.

Definitely, I have to rewrite DMAC with AVALON bus.

[SueC_Altera]

Hi Manprocoder,

We checked internally, and we don't have expertise on the active_asconIP, so we aren't able to help.  I hope there is community help available.  Have you checked with the owner of the IP?

Sue

[Manprocoder]

Hi @SueC,
I do not think the problem lies in my IP.
I rewrite DMAC with Avalon bus and everything is well during run-time duration.
So, I state that interconnect does not support AXI4 burst (quartus 18.1).

[SueC_Altera]

Hi Manprocoder,

I checked with engineering and they checked the code base for 18.1 interconnect modules and found that AXI4 does support the burst logic as described in the 18.1 UG: https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/burst-support.html

Please help me understand why you think the problem is in the interconnect?

Thanks,

Sue

[Manprocoder]

Hi @SueC_Altera 

To be completely upfront, the reasons why I conclude my issue that lies in the interconnect are as follows:
+ The first reason: I rewrite DMAC with Avalon bus, everything is well (read and write occur smoothly)

+ The second one:  AXI4 DMAC runs well with READ burst, but the same does not happen to WRITE burst. (My IP issues request, AWVALID is active)

I only assume my problem like this, but I'm not sure 100%.

Best Regards,

[SueC_Altera]

Hi Manprocoder,

Are you able to provide your design for us to look at?

Sue

[Manprocoder]

Hi @SueC_Altera 

Sure.

My design is in the link below.

https://drive.google.com/drive/folders/1vUU7XVqdJSXgnn0ZmVu3jjvk3DmLEOFW?usp=drive_link

[SueC_Altera]

Thanks, Manprocoder. We'll get back to you.

Sue

[BoonBengT_Altera]

Hi @Manprocoder,

This it to let you know that we are still working on your request.

Will get back to you at earliest.

Thank you so much for your patients.

Best Wishes

BB

[Manprocoder]

Hi @BoonBengT_Altera
To be completely upfront, I have struggled to find a solution to my issue for 2 weeks before posting it to your forum. But, now, I have no time for it, so, I must turn into Avalon bus.
Thanks for your energetic support and enthusiasm.
Best wishes,
Man

[BoonBengT_Altera]

Hi @Manprocoder,

Good to know and appreciate you sharing your updates from your end.

Hi @SueC_Altera,

Just checking in if there is any updates from your end.

Hope to hear from you soon.

Best Wishes

BB

[SueC_Altera]

Hi Manprocoder,

I've asked our engineering team to look at this issue.  We tried running your design in simulation and it got hung with no awvalid or arvalid asserted. They then created a separate design that uses the AXI4 1x1 bridge with Interconnect (Data width: 32b to 64b) and HDL generated in Quartus18.1std. Everything worked fine in this design. 

I'm asking to see if we can share this design with you.

Sue