Re: Access-duration between reading 2 time from a perepherial

Altera_Forum · ‎04-15-2011

Hi Folks,

i implemented a RTC with an resolution of 8 ns with an memory-mapped avalon-interface for reading the timestamps.

if i read from this device with nios II/f 2 times, the difference between them

is 632-720 nanoseconds. The application is built on MicroC/OS II.

They are running in 2 different Clock-Domains Timer(125 MHz), NIOS runs with 100 MHz. Domaincrossing without Clock-Crossing-Bridge, generated by Avalon-Interconnect-Fabrik. Main-Memory is DDR2-RAM in Halfdatarate 100 MHz, high performance cotroller 1. The Board is an Stratix II GX PCI Devikit. Cache 4 Kbyte, Data Cache 2 Kbyte.

here is the sourcecode
//The Call
OS_ENTER_CRITICAL();
    messure_avalon(PTPCORE_0_BASE);
OS_EXIT_CRITICAL();
-- THE Function
int messure_avalon(alt_u32 base){
TIME_STAMP* ts1 = (TIME_STAMP*) malloc(sizeof(TIME_STAMP));
TIME_STAMP* ts2 = (TIME_STAMP*) malloc(sizeof(TIME_STAMP));
ts1->seconds =  IORD_PTPCORE_PRESENT_SECONDS(base);
ts1->nanoseconds =  IORD_PTPCORE_PRESENT_NANOSECONDS(base);
//printf("hallo hallo");
ts2->seconds =  IORD_PTPCORE_PRESENT_SECONDS(base);
ts2->nanoseconds =  IORD_PTPCORE_PRESENT_NANOSECONDS(base);
printf("second-diff: %i\n", ts2->seconds - ts1->seconds);
printf("nanosecs-diff: %i\n", ts2->nanoseconds - ts1->nanoseconds);
free(ts1);
free(ts2);
return 0;
}
(Reading from Seconds, making an snapshot of nanoseconds.)

My question is the delay of 632-720 ns in the right range, how can i measure or estimate it ? Any suggestions. its round about 79-90 cycles, its

a lot in my opinion. 40-45 cycles per read, and store to ddr2.

Thank you so far

best regards

Mooresstudent

Altera_Forum · ‎04-18-2011

Have you any interrupts in your system that are still active?

The malloc'ed memory might be another reason for a jitter ... maybe depending on what memory is cached and not.

Altera_Forum · ‎04-18-2011

hi Karsten,

in my opinion OS_ENTER_CRITICAL(); disable all interrupts. and the malloc is out of the measurement, only accessing the malloc memory. and my NIOS II run with 100 MHz so there are only 63-72 cycles -> 31 - 37 cycles per read and store.

seems to be a lot of time.

so far

mooresstudent

Altera_Forum · ‎04-19-2011

You are right about OS_ENTER_CRITICAL(). Interrupts can not cause the jitter.

Altera_Forum · ‎04-19-2011

Hi,

what's your compiler optimization level ? Compiler setting 0 (off) generates a lot of code. You should set it to Level2.

Altera_Forum · ‎04-27-2011

thank a lot for your replys.

I changed the optimizationlvl from 0 to 3. And use the register prefix for storing the time.

now the function looks like:


int messure_avalon(alt_u32 base){
register int sekunden1, sekunden2;
register int nsekunden1, nsekunden2;
sekunden1 =  IORD_PTPCORE_PRESENT_SECONDS(base);
nsekunden1 =  IORD_PTPCORE_PRESENT_NANOSECONDS(base);
sekunden2 =  IORD_PTPCORE_PRESENT_SECONDS(base);
nsekunden2 =  IORD_PTPCORE_PRESENT_NANOSECONDS(base);
printf("second-diff: %i\n", sekunden2 - sekunden1);
printf("nanosecs-diff: %i\n", nsekunden2 - nsekunden1);
return 0;
}

U can find the Dissassembly at

http://pastebin.com/j1ezxh91


sekunden2 =  IORD_PTPCORE_PRESENT_SECONDS(base); expands to
0x0201bb08 <messure_avalon+60>:  ldw   r2,-4(fp)
0x0201bb0c <messure_avalon+64>:  addi  r2,r2,20
0x0201bb10 <messure_avalon+68>:  ldwio r2,0(r2)
0x0201bb14 <messure_avalon+72>:  mov   r3,r2

so before the ldwio-call there are 2 instructions (i estimate 1 cycle per instruction).

now it prints 576-592 ns. 28 - 30 cycles per read, still a lot. 2 cycles for the instructions, 2 cycles in my component for snapshotting. There are still 24 cycles for clock crossing and avalon-arbitration :confused:.

kind regards

mooresstudent

Altera_Forum · ‎05-12-2011

We are seeing the same performance issue in our development (haven't optimized our code much but our performance is about 60 cycles per read).

Is this latency normal for avalon interface or is it that we did something wrong in the configuration of the SOPC system/Avalon interface?

Thanks,

Hua