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I have a custom board with the 88E111 Ethernet PHY. At one point, the board would light up LEDs indicating a link has been made and it was in 100 mode.
I did not change my design at all, but now I can't make a link. This first happened when I tried to plug the board directly into the LAN from the wall, rather than through the switch, in an attempt to get DHCP to work. I now have the board connected to a switch which goes to a PC and company LAN. The lights on the switch indicate that there is a physical connection made on the port the board is plugged into. They blink with 10 mode activity. But, the board doesn't indicate a link. Running the simple socket server design produces this output:
prepped 1 interface, initializing...
INFO : TSE MAC 0 found at address 0x08000000
INFO : PHY Marvell 88E1111 found at PHY address 0x12 of MAC Group
INFO : PHY - Automatically mapped to tse_mac_device
INFO : PHY - Restart Auto-Negotiation, checking PHY link...
WARNING : PHY - Auto-Negotiation FAILED
MARVELL : Enabling auto crossover
MARVELL : PHY reset
MARVELL : Mode changed to RGMII/Modified MII to Copper mode
MARVELL : Enable RGMII Timing Control
MARVELL : PHY reset
INFO : PHY - Checking link...
INFO : PHY - Link not yet established, restart auto-negotiation...
INFO : PHY - Restart Auto-Negotiation, checking PHY link...
WARNING : PHY - Auto-Negotiation FAILED
WARNING : PHY - Link could not established
WARNING : PHY - Auto-Negotiation not completed! Speed = 100, Duplex = Full
OK, x=0, CMD_CONFIG=0x00000000
I am completely stumped on how I can't even make a link now, without changing any hardware or software. Before moving cables to plug the board directly into the wall, it would pass the auto negotiation and then fail at DHCP. I have gone back to the original setup exactly but the result is the same. No link at all.
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You're sure the cable is connected correctly? Auto-Negotiation is a property of the PHY itself. You receive this value via MDIO interface, so it's MDI side problem.
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--- Quote Start --- You're sure the cable is connected correctly? Auto-Negotiation is a property of the PHY itself. You receive this value via MDIO interface, so it's MDI side problem. --- Quote End --- Yes, also I've switched cables to be sure. Do you think I may have a broken connector? I've also tried the setup in a completely different lab with different cable, switch, and wall connection and it did not make a difference.
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Do you use DHCP or Static IP.....in your pc?
If you use DHCP....try to use a Static IP....- Mark as New
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I built a new board with a different LAN connector and I'm still having the exact same issue. It worked all day, now nothing.
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I seem to have fixed the problem, hopefully permanently, by adding a 100 clock cycle delay til I drive the ethernet PHY reset line high when the board powers up.
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--- Quote Start --- I seem to have fixed the problem, hopefully permanently, by adding a 100 clock cycle delay til I drive the ethernet PHY reset line high when the board powers up. --- Quote End --- Is it Marvell 88E1111 chip? Did You read the datasheet then? It needs about 50ms reset after power up. Kinda annoying bug.
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I think this was more than 50ms according to my experience.
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--- Quote Start --- I have a custom board with the 88E111 Ethernet PHY. At one point, the board would light up LEDs indicating a link has been made and it was in 100 mode. I did not change my design at all, but now I can't make a link. This first happened when I tried to plug the board directly into the LAN from the wall, rather than through the switch, in an attempt to get DHCP to work. I now have the board connected to a switch which goes to a PC and company LAN. The lights on the switch indicate that there is a physical connection made on the port the board is plugged into. They blink with 10 mode activity. But, the board doesn't indicate a link. Running the simple socket server design produces this output:
prepped 1 interface, initializing...
INFO : TSE MAC 0 found at address 0x08000000
INFO : PHY Marvell 88E1111 found at PHY address 0x12 of MAC Group
INFO : PHY - Automatically mapped to tse_mac_device
INFO : PHY - Restart Auto-Negotiation, checking PHY link...
WARNING : PHY - Auto-Negotiation FAILED
MARVELL : Enabling auto crossover
MARVELL : PHY reset
MARVELL : Mode changed to RGMII/Modified MII to Copper mode
MARVELL : Enable RGMII Timing Control
MARVELL : PHY reset
INFO : PHY - Checking link...
INFO : PHY - Link not yet established, restart auto-negotiation...
INFO : PHY - Restart Auto-Negotiation, checking PHY link...
WARNING : PHY - Auto-Negotiation FAILED
WARNING : PHY - Link could not established
WARNING : PHY - Auto-Negotiation not completed! Speed = 100, Duplex = Full
OK, x=0, CMD_CONFIG=0x00000000
I am completely stumped on how I can't even make a link now, without changing any hardware or software. Before moving cables to plug the board directly into the wall, it would pass the auto negotiation and then fail at DHCP. I have gone back to the original setup exactly but the result is the same. No link at all. --- Quote End --- So did you finally solved this issue? I'm having the same exact message and running out of options. Thanks!
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I am now having the same problem as you did
Have you ever fiugred it out ?- Mark as New
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--- Quote Start --- I am now having the same problem as you did Have you ever fiugred it out ? --- Quote End --- Yes, what worked for me was as dumb as upgrading to quartus 13.1. Altera even knows about the IP bugs on 13.0 but they don't tell you until you voice your frustration. I spent at least a week debugging this issue and all I needed was a SW upgrade :mad:
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But I use quartus 14.0. Also appear this messge. Have you fiugred it out?
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--- Quote Start --- I seem to have fixed the problem, hopefully permanently, by adding a 100 clock cycle delay til I drive the ethernet PHY reset line high when the board powers up. --- Quote End --- I am facing exactly the same error. Could you tell me steps that how you added 100 clock cycle delay to resolve this issue. I am using Quartus 15.1 and Altera DE2-115 board.
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I have got the same issue. I am getting the following error :
*******************************************************************
InterNiche Portable TCP/IP, v3.1
Copyright 1996-2008 by InterNiche Technologies. All rights reserved.
altera_eth_tse_init 0
prep_tse_mac 0
Your Ethernet MAC address is 00:07:ed:ff:e2:d0
Static IP Address is 192.168.1.234
prepped 1 interface, initializing...
tse_mac_init 0
List of PHY profiles supported (Total profiles = 5)...
Profile No. 0 :
PHY Name : Marvell 88E1111
PHY OUI : 0x005043
PHY Model Num. : 0x0c
PHY Rev. Num. : 0x02
Status Register : 0x11
Speed Bit : 14
Duplex Bit : 13
Link Bit : 10
Profile No. 1 :
PHY Name : Marvell Quad PHY 88E1145
PHY OUI : 0x005043
PHY Model Num. : 0x0d
PHY Rev. Num. : 0x02
Status Register : 0x11
Speed Bit : 14
Duplex Bit : 13
Link Bit : 10
Profile No. 2 :
PHY Name : National DP83865
PHY OUI : 0x080017
PHY Model Num. : 0x07
PHY Rev. Num. : 0x0a
Status Register : 0x11
Speed Bit : 3
Duplex Bit : 1
Link Bit : 2
Profile No. 3 :
PHY Name : National DP83848C
PHY OUI : 0x080017
PHY Model Num. : 0x09
PHY Rev. Num. : 0x00
Status Register : 0x00
Speed Bit : 0
Duplex Bit : 0
Link Bit : 0
Profile No. 4 :
PHY Name : Intel PEF7071
PHY OUI : 0x355969
PHY Model Num. : 0x00
PHY Rev. Num. : 0x01
Status Register : 0x00
Speed Bit : 0
Duplex Bit : 0
Link Bit : 0
INFO : TSE MAC 0 found at address 0x08000800
INFO : Multi Channel = No
INFO : MDIO Shared = No
INFO : MAC Type = 10/100/1000 Ethernet MAC
INFO : MAC Address = 0x08000800
INFO : MAC Device = tse_mac_device[0]
INFO : PHY Marvell 88E1111 found at PHY address 0x00 of MAC Group[0]
INFO : PHY OUI = 0x005043
INFO : PHY Model Number = 0x0c
INFO : PHY Revision Number = 0x2
INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]
INFO : PHY[0.0] - Advertisement of 1000 Base-T Full Duplex set to 1
INFO : PHY[0.0] - Advertisement of 1000 Base-T Half Duplex set to 1
INFO : PHY[0.0] - Advertisement of 100 Base-T4 set to 0
Created "Inet main" task (Prio: 2)
INFO : PHY[0.0] - Advertisement of 100 Base-TX Full Duplex set to 1
INFO : PHY[0.0] - Advertisement of 100 Base-TX Half Duplex set to 1
INFO : PHY[0.0] - Advertisement of 10 Base-TX Full Duplex set to 1
INFO : PHY[0.0] - Advertisement of 10 Base-TX Half Duplex set to 1
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
INFO : Applying additional PHY configuration of Marvell 88E1111
INFO : Applying additional user PHY configuration
MARVELL : Mode changed to RGMII/Modified MII to Copper mode
MARVELL : Enable RGMII Timing Control
MARVELL : PHY reset
INFO : PHY[0.0] - Checking link...
INFO : PHY[0.0] - Link not yet established, restart auto-negotiation...
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
WARNING : PHY[0.0] - Auto-Negotiation FAILED
*************************************************************************************************
I have been trying to implement Nios II simple socket server from the reference design : https://fpgacloud.intel.com/devstore/platform/16.0.0/Standard/nios-ii-simple-socket-server-ethernet-example-for-cvgt/
I was able to setup everything and start downloading the Nios II software project to the board. But while doing so, I am facing this auto negotiation failed warning. i am unable to decide whether the connection to the board was established or not. I have disabled the DHCP and given the address 192.168.1.234 in the simple_socket_server.h file. I have been following the steps mentioned in the document : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/tt/tt_nios2_tcpip.pdf
Previosly i have implemented CVGT Simple_Socket_Server from the document https://www.intel.com/content/dam/altera-www/global/en_US/uploads/9/97/CVGT_Simple_Socket_Server_Design_Example.pdf where I have used the static IP for TCP/IPv4 with the IP address 192.168.1.1 . It worked fine. Kindly help me with the Auto negotiation error . I have uploaded the relevant screenshots in the NIOS II SBT. Thank You.
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--- Quote Start ---
I seem to have fixed the problem, hopefully permanently, by adding a 100 clock cycle delay til I drive the ethernet PHY reset line high when the board powers up.
--- Quote End ---
I am facing the same issue. Can you elaborate where should we add 100 clock cycle delay?
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Any luck resolving this?
I had this working on DE2-115 board with the SSS example using Quartus 17.0 and SGDMA; however, upgrading to Quartus 17.1 and now NIOS II SBT BSP requires the mSGDMA module. So I've migrated to mSGDMA... everything builds and runs just fine, but now auto-negotiaton fails.
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