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DMA Controller

Altera_Forum
Honored Contributor II
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Does the DMA Controller support streaming byte datawidths from a peripheral to word datawidths for memory? In other words does it support the avalon bus capability of mixing the two bus sizes. Where it will buffer 4 bytes then does a single memory write.

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Altera_Forum
Honored Contributor II
396 Views

Guess no one knows...

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Altera_Forum
Honored Contributor II
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Hi, I do the reverse without problems. I take word values out of SDRAM (it's a 32 bit SDRAM) and stuff them out to an 8 bit port. It all seems to work ok.  

Bart
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Altera_Forum
Honored Contributor II
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jasonm, 

I'm not completely sure I understand your question, but I'll take a stab at it: 

 

DMA transfers go at whatever data size is specified in the control register. If you read from a 32-bit SDRAM and write to an 8-bit peripheral (say, a UART), you'd set the control register BYTE bit, and both reads and writes would be done byte-by-byte. 

 

So, 

"In other words does it support the avalon bus capability of mixing the two bus sizes" - Yes. 

"Where it will buffer 4 bytes then does a single memory write" - No.
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Altera_Forum
Honored Contributor II
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I want the most efficient memory usage possible. So I'd like all the reads/writes to memory to use the full 32 bit datawidth. The problem is my peripheral has an 8bit databus. Initially I set the datawidth for the dma streaming to 8bit during testing and it worked fine. The main question was whether it would automatically buffer 4 bytes of those to maximize the memory efficiency. I don't want to waste memory cycles by only writing a byte during every cycle. I'd rather redesign the paripheral so that it would buffer 4 bytes and then do 32 bit transfers. Before I do that I wanted to make sure that it wasn't already being done automatically.

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Altera_Forum
Honored Contributor II
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Right, sorry, at present the DMA controller wastes memory bandwidth in the way you describe. 

 

Giving your peripheral a 32-bit data width and dealing with the individual bytes internally is a good solution. 

 

In the future perhaps the DMA controller will be made smarter, or some sort of datawidth-matching, caching bridge component will be created.
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