Data acquisition at both edge of the clock: Signal Tap logic II analyzer

[Altera_Forum]

Hi, 

can Signal Tap II logic Analyzer be used for data acquisition at both rising and falling edge of the clock? I need it for test purpose.  I am using TSE MAC in RGMII mode. When I put Signal Tap logic II analyzer, I have data only at one edge(not both rising and falling edge).  Is there any additional setting in Signal Tap II logic Analyzer which has to be done for data acquisition at both rising and falling edge of the clock?  Any help?

[Altera_Forum]

Hi, 

 I think by doubling frequency of sample clock being used in Signal Tap analyzer you can achieve your goal. I mean using PLL, generate one clock having frequency double than what you are using currently and use that PLL output as sampling clock in signal tap.  Cheers, Bhaumik