Download NIOS_Software from FLASH to SDRAM with Bootloader on On-Chip-Memory

[Altera_Forum]

Hi all, 

  i have a problem with downloading a nios-software (c-program) from flash-memory to an sdram with help of a bootloader lies on on-chip-ram    general requirements:     NIOSII CPU --> BASE_ADR 0x00080800 END 0x00080FFF  ONCHIP-MEMORY -> BASE_ADR 0x00080200 END 0x000803FF  FLASH-MEM --> BASE_ADR 0x11000000 END 0x11FFFFFF  SDRAM-Controller --> BASE_ADR 0x08000000 END 0x0FFFFFFF      alignment (http://dict.leo.org/ende?lp=ende&p=ci4ho3kmaa&search=alignment&trestr=0x801):    - NIOSII/s   o RESET_VECTOR --- ONCHIP-MEMORY --- OFFSET 0x0 (0x00080200)  o EXCEPTION_VECTOR --- SDRAM_0 --- OFFSET 0x20 (0x08000020)    - On-Chip-Memory  o ROM  o Data Width 32  o MEM-Size 512 Bytes  o .hex – file with is load boot_rom.hex  § This file is the example “small_boot_copier” BOOTLOADER from ALTERA (http://www.altera.com/literature/an/an458.pdf)    accomplishment (http://dict.leo.org/ende?lp=ende&p=ci4ho3kmaa&search=accomplishment&trestr=0x8001) in NIOSII command shell (9.1):    1) make all FLASH_BASE=0x11000000 BOOT_IMAGE_OFFSET=0x00600000 CODE_BASE=0x080000000     BOOT_IMAGE_OFFSET: it is right or 0x11600000 ???  CODE_BASE: means it, that it is the address on SDRAM where the NIOS C-Software lies ?    2) To program the flash, I use the following command    Nios2-falsh-programmer –cable=”Usb-Blaster [USB-0]” –base=0x11000000 nios_software.flash    Both commands run fine.    BUT: when I reset the nios-processor, the software don’t run  Can somebody help me please, to cancel my mistakes?    Thank you

[Altera_Forum]

I would be happy if someone could help me. 

 :)  Thank you

[Altera_Forum]

I'm booting from serial flash device (EPCS). The reset vector points to the epcs_controller which contains a small onchip ram (see attached jpg). In that RAM is the boot copier or bootloader which copies the Nios program from serial flash to the SDRAM. After that that the programm is called by the bootloader. 

Your reset vector should point to the bootloader code. Have you the source code of the bootloader? Than you can debug the code and see if the flash content will be copied to the SDRAM.  Jens

[Altera_Forum]

Thank you for your reply. 

 I have point my reset_vector to the bootloader code. But i can not debug the bootloader code because the code is on chip memory. What kind of bootloader does you use? Steve

[Altera_Forum]

Steve, please have a look at 

http://www.alteraforum.com/forum/showthread.php?t=23447 (http://www.alteraforum.com/forum/showthread.php?t=23447)  There is my bootloader project. You can create a new (blank) software project in the Nios IDE and put the bootloader sources in that. Now you can debug this code over JTAG.  The bootloader is based on Altera bootloader (C:\altera\91\nios2eds\components\altera_nios2\boot_loader_sources). The difference is that the modified bootloader boots from a fixed address (defined in boot_loader.h)  Jens

[Altera_Forum]

I'll just read the posts. Previously I've still a question of principle. 

 I have no EPCS device on my FPGA-development board.  - For downloading the FPGA-Firmware from flash to the fpga, i use a CPLD device  - to download the nios-firmware from flash to NIOSII-processor i'll use the bootloader  - the bootloader have to copy the nios-firmware data to the SDRAM  -finally when i reset my fpga-firmware, the current firmware should automatically run as well as I would load the firmware via jtag   Does the bootloader works on this conditions ?  Thank you 

[Altera_Forum]

If you have a CFI flash than you couldn't use this bootloader. I don't have experience with parallel flash but there are several example projects from Altera where Nios is booting from CFI flash. They use also a CPLD (called config controller). Please have a look at these examples: 

 C:\altera\72\nios2eds\examples\vhdl\niosII_cycloneII_2c35\standard C:\altera\72\nios2eds\examples\vhdl\niosII_stratixII_2s60_RoHS\standard   Jens