Failed to boot NIOS II app from S25FL128SAGNFM001 using Intel GSFI

[BBS3000]

Hello,

I am having troubles with booting up a Cyclone V NIOS II app from S25FL128SAGNFM001 using Intel GSFI. I am using 22.1 tools.

I tried to follow the https://community.intel.com/cipcp26785/attachments/cipcp26785/fpga-wiki/926/1/Generic_Serial_Flash_Interface_design_example_quick_start_guide_final_updated.pdf

but have no luck. Sorry for a very long post. 

Here is the Platform Designer NIOS setup

Here is the Intel GSFI /Flash setup

The NIOS application runs from the RAM and accesses the flash with no problems (for some reason my app reports Control Register = 0x82 instead of 0x101) but I cannot boot it from the flash.

Here are the BSP settings

Here is the mem_init_generate output (only serial_flash_top_0.hex is used)

17:02:22 **** Build of configuration Nios II for project app ****

wsl make mem_init_generate

Info: Building /mnt/c/Work/Projects/app/Cyclone_V/app_bsp/

make --no-print-directory -C /mnt/c/Work/Projects/app/Cyclone_V/app_bsp/

[BSP build complete]

Post-processing to create mem_init/boot_rom.hex...

elf2hex.exe app.elf 0x00018000 0x0001afff --width=32 --little-endian-mem --create-lanes=0 mem_init/boot_rom.hex

Post-processing to create mem_init/cycloneIII_3c25_ept_with_niosII_sopc_onchip_memory2_0.hex...

elf2hex.exe app.elf 0x00010000 0x00014fff --width=32 --little-endian-mem --create-lanes=0 mem_init/cycloneIII_3c25_ept_with_niosII_sopc_onchip_memory2_0.hex

Post-processing to create mem_init/serial_flash_top_0.hex...

alt-file-convert.exe -I elf32-littlenios2 -O hex --input=app.elf --output=mem_init/serial_flash_top_0.hex --base=0x03000000 --end=0x03ffffff --reset=0x03800000 --out-data-width=8 --boot="C:\intelfpga_lite\22.1std\nios2eds\components\altera_nios2\boot_loader_cfi.srec"

Converting Nios II ELF file to HEX file. Appending boot file.

Post-processing to create mem_init/hdl_sim/async_512Kx32.dat...

elf2dat --infile=app.elf --outfile=mem_init/hdl_sim/async_512Kx32.dat \

                        --base=0x00400000 --end=0x005fffff --width=32 \

                        --little-endian-mem --create-lanes=0

Post-processing to create mem_init/hdl_sim/boot_rom.dat...

elf2dat --infile=app.elf --outfile=mem_init/hdl_sim/boot_rom.dat \

                        --base=0x00018000 --end=0x0001afff --width=32 \

                        --little-endian-mem --create-lanes=0

Post-processing to create mem_init/hdl_sim/cycloneIII_3c25_ept_with_niosII_sopc_onchip_memory2_0.dat...

elf2dat --infile=app.elf --outfile=mem_init/hdl_sim/cycloneIII_3c25_ept_with_niosII_sopc_onchip_memory2_0.dat \

                        --base=0x00010000 --end=0x00014fff --width=32 \

                        --little-endian-mem --create-lanes=0

Post-processing to create mem_init/hdl_sim/ssram_0.dat...

elf2dat --infile=app.elf --outfile=mem_init/hdl_sim/ssram_0.dat \

                        --base=0x00600000 --end=0x006fffff --width=32 \

                        --little-endian-mem --create-lanes=1

Post-processing to create mem_init/hdl_sim/async_512Kx32.sym...

nios2-elf-nm.exe -n app.elf > mem_init/hdl_sim/async_512Kx32.sym

Post-processing to create mem_init/hdl_sim/boot_rom.sym...

nios2-elf-nm.exe -n app.elf > mem_init/hdl_sim/boot_rom.sym

Post-processing to create mem_init/hdl_sim/cycloneIII_3c25_ept_with_niosII_sopc_onchip_memory2_0.sym...

nios2-elf-nm.exe -n app.elf > mem_init/hdl_sim/cycloneIII_3c25_ept_with_niosII_sopc_onchip_memory2_0.sym

Post-processing to create mem_init/hdl_sim/ssram_0.sym...

nios2-elf-nm.exe -n app.elf > mem_init/hdl_sim/ssram_0.sym

I combine FPGA sof file and NIOS hex file into common jic file.

Any help will be greatly appreciated.

Thanks!

[JingyangTeh]

Hi

I see that your linker setting is wrong in the BSP Setting.

You are running the "Nios II processor application is copied from EPCQ flash to RAM using boot copier" boot method.

Could you change the Linker to all OnChip Memory.

https://www.intel.com/content/www/us/en/docs/programmable/683104/current/bsp-editor-settings.html

Regards

Jingyang, Teh

[BBS3000]

Hi,

Thank you for your reply.

The OnChip memory is too small to copy there the application.

The async_512Kx32 is an external RAM that is used for running the application.

It works since the debugger loads the app there without any problems.

Thanks.

[JingyangTeh]

Hi

I this case, you would need to change the exception vector to select the external RAM instead of the on chip memory.

Additional info, if you have spare logic space in the FPGA, you could increase the on chip memory size to fit your application. You could remove the need of external RAM.

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Do you still have any other question regarding your issue?

Regards

Jingyang, Teh

[BBS3000]

Hi,

The issue was due to a missed byte-enable signal to the SRAM so the bootloader could not copy bytes from the flash to the SRAM correctly. We fixed it.

Thank you!

[JingyangTeh]

Hi

I’m glad that your question has been addressed, I will now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh