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How floating point numbers are handled in NIOS processor ? Do I have to use seperate registers for both mantissa & exponent? How a two dimensional array (each element is a floating number) is accessed in Verilog ?
--- Quote Start --- originally posted by mohana sundaram.s.v+aug 26 2005, 09:14 am--><div class='quotetop'>quote (mohana sundaram.s.v @ aug 26 2005, 09:14 am)</div>
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how floating point numbers are handled in nios processor?[/b]
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niosii does not have an fpu. floating point is done in software. that said, some people have done floating-point coprocessors, but i haven't used any of them, so i can't say.
if you're looking to do heavy-duty floating point, you might want to generate a custom peripheral (either with bus mastering, or with extra slave ports for altera dma peripherals to use) to do the job. this sounds like it is more in the realm of megacore ip blocks and dsp builder.
<!--quotebegin-mohana sundaram.s.v@Aug 26 2005, 09:14 AM how a two dimensional array (each element is a floating number) is accessed in verilog ? --- Quote End --- That would be a three-dimensional 'reg' array (rows, columns, and bits). Altera's Verilog implementation is crippled in that it does not support multidimensional register arrays (except in the limited case of one-dimensional memory spaces). Again, DSP Builder handles this a bit better.
